[PATCH v2] mtd: spi-nor: core: Check read CR support

[Pratyush Yadav]

On Fri, Sep 19 2025, Jakub Czapiga wrote:

> Some SPI controllers like Intel's one on the PCI bus do not support
> opcode 35h. This opcode is used to read the Configuration Register on
> SPI-NOR chips that have 16-bit Status Register configured regardless
> of the controller support for it. Adding a check call in the setup step
> allows disabling use of the 35h opcode and falling back to the manual
> Status Registers management.
>
> Before:
> openat(AT_FDCWD, "/dev/mtd0", O_RDWR)   = 4
> ioctl(4, MIXER_WRITE(6) or MEMUNLOCK, {start=0, length=0x2000000}) = -1
> EOPNOTSUPP
>
> After:
> openat(AT_FDCWD, "/dev/mtd0", O_RDWR)   = 4
> ioctl(4, MIXER_WRITE(6) or MEMUNLOCK, {start=0, length=0x2000000}) = 0
> ioctl(4, MIXER_WRITE(5) or MEMLOCK, {start=0x1800000, length=0x800000}) = 0
>
> Suggested-by: Adeel Arshad <adeel.arshad at intel.com>
> Signed-off-by: Jakub Czapiga <czapiga at google.com>

Reviewed-by: Pratyush Yadav <pratyush at kernel.org>

Applied to spi-nor/next. Thanks!

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-- 
Regards,
Pratyush Yadav