[PATCH v2 6/6] mtd: spi-nor: core: avoid odd length/address writes in 8D-8D-8D mode

[Pratyush Yadav]

On Tue, Jul 01 2025, Luke Wang wrote:

>> > On Mon, May 12 2025, Miquel Raynal wrote:
>> >
>> > > Hello,
>> > >
>> > > On 07/05/2025 at 09:43:25 GMT, Pratyush Yadav <pratyush at kernel.org>
[...]
>> > >
>> > > The fact is that we will have octal DTR support in SPI NAND as well at
>> > > some point, hence a common solution would be welcome as we will likely
>> > > face similar problems when performing these unaligned accesses. I
>> > > don't know how feasible it is yet, but if we have a fix for SPI NOR,
>> > > we will need something similar for SPI NAND.
[...]
>
> Sorry for delayed response.
>
> After reviewing the SPI NAND driver, I noticed that the addr and len
> alignment has already been implemented in spinand_read_from_cache_op()
> and spinand_write_to_cache_op() functions.

Right. I took a very quick look as well and it seems that SPI NAND only
does page sized reads and writes in spinand_write_to_cache_op() and
spinand_read_from_cache_op(). So it should not be a problem.

Miquel, Luke sent a respin [0] for fixing this in SPI NOR and I need to
decide if I should take them or push for a more generic fix. Did I miss
some place where SPI NAND can do odd-length reads or writes? If not, I'd
rather just take the respinned patches.

>
> Additionally, using 0xff padding in spi_mem_dirmap_write() might not
> be suitable for non-flash memory devices.

NAND also seems to be using 0xff though. From spinand_write_to_cache_op():

	nbytes = nanddev_page_size(nand) + nanddev_per_page_oobsize(nand);
	memset(spinand->databuf, 0xff, nanddev_page_size(nand));

Anyway, if needed we can solve that with a field in struct
spi_mem_dirmap_info I guess.

[0] https://lore.kernel.org/linux-mtd/20250708091646.292-1-ziniu.wang_1@nxp.com/T/#u

-- 
Regards,
Pratyush Yadav