[PATCH v2 2/3] dt-bindings: dma: snps,dw-axi-dmac: add dma-coherent property

[Rob Herring (Arm)]

On Wed, 03 Dec 2025 07:47:34 +0800, Khairul Anuar Romli wrote:
> The Synopsys DesignWare AXI DMA Controller on Agilex5, the controller
> operates on a cache-coherent AXI interface, where DMA transactions are
> automatically kept coherent with the CPU caches. In previous generations
> SoC (Stratix10 and Agilex) the interconnect was non-coherent, hence there
> is no need for dma-coherent property to be presence. In Agilex 5, the
> architecture has changed. It  introduced a coherent interconnect that
> supports cache-coherent DMA.
> 
> Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli at altera.com>
> ---
> Changes in v2:
>         - Rephrase commit message to describe why the property is needed now
>           and was not needed previously.
>         - Remove redundant statement.
> ---
>  Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml | 2 ++
>  1 file changed, 2 insertions(+)
> 

Reviewed-by: Rob Herring (Arm) <robh at kernel.org>