[PATCH v2] mtd: nand: raw: atmel: Respect tAR, tCLR in read setup timing

[Sverdlin, Alexander]

Hi Alexander,

On Mon, 2025-08-25 at 13:02 +0200, Alexander Dahl wrote:
> > Having setup time 0 violates tAR, tCLR of some chips, for instance
> > TOSHIBA TC58NVG2S3ETAI0 cannot be detected successfully (first ID byte
> > being read duplicated, i.e. 98 98 dc 90 15 76 14 03 instead of
> > 98 dc 90 15 76 ...).
> > 
> > Atmel Application Notes postulated 1 cycle NRD_SETUP without explanation
> > [1], but it looks more appropriate to just calculate setup time properly.
> > 
> > [1] Link: https://ww1.microchip.com/downloads/aemDocuments/documents/MPU32/ApplicationNotes/ApplicationNotes/doc6255.pdf
> > Cc: stable at vger.kernel.org
> > Fixes: f9ce2eddf176 ("mtd: nand: atmel: Add ->setup_data_interface() hooks")
> > Signed-off-by: Alexander Sverdlin <alexander.sverdlin at siemens.com>
> 
> Tested-by: Alexander Dahl <ada at thorsis.com>
> 
> Threw this on top of 6.12.39-rt11 and tested on two custom platforms
> both with a Spansion S34ML02G1 SLC 2GBit flash chip, but with
> different SoCs (sama5d2, sam9x60).  We had difficulties with the
> timing of those NAND flash chips in the past and I wanted to make sure
> this patch does not break our setup.  Seems fine in a quick test,
> reading and writing and reading back is successful.

thank you for your feedback!

Do you see an opportunity to drop the downstream timing quirks with my patch?
I actually have another patch related to timings, but it's based on code-review
only and the theoretical issue never manifested itself in practice on our side...
(it's about missing ndelay at the end of atmel_smc_nand_exec_instr())

Regards,
-- 
Alexander Sverdlin
Siemens AG
www.siemens.com