[spi-nor] Macronix MX25L requires CR read opcode 0x15 (not 0x35)

[Maarten Zanders]

Hi all,

On the Macronix MX25L12833F (ID 0xC22018) & others of this family/mfg,
the CR (condition register) must be read with opcode 0x15. The driver
currently uses 0x35, which the chip does not recognize.

Datasheet: https://www.macronix.com/Lists/Datasheet/Attachments/8934/MX25L12833F,%203V,%20128Mb,%20v1.0.pdf
(p.27, RDCR).

With 0x35 the data line floats and the driver reads CR as 0xFF
(depending on previous state of the line or pull up/down). This value
is then written back in spi_nor_write_16bit_sr_and_check(), setting CR
to 0xFF. One consequence is flipping the OTP Top/Bottom protection
bit, so from then on, locking the top block actually locks the bottom
sector. This breaks bootloader updates (in my case) and similar flows.

Possible fixes:
- Make CR read opcode configurable per device.
- Force Macronix parts to 8-bit SR accesses (clear SNOR_F_HAS_16BIT_SR).
- Implement T/B bit handling for Macronix (needed for already-fielded
devices with flipped OTP bit, but complicated by non-uniform
protection blocks).

What would be the preferred approach? Other ideas? Anyone seen similar
with Macronix parts?
A quick fix which can be backported easily and the full implementation
later on would be beneficial IMHO.

Thanks,
Maarten