[PATCH v12 6/8] spi: spi-qpic: add driver for QCOM SPI NAND flash Interface

[kernel test robot]

Hi Md,

kernel test robot noticed the following build warnings:

[auto build test WARNING on mtd/nand/next]
[also build test WARNING on broonie-spi/for-next robh/for-next linus/master v6.12-rc4 next-20241025]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Md-Sadre-Alam/spi-dt-bindings-Introduce-qcom-spi-qpic-snand/20241021-200849
base:   https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git nand/next
patch link:    https://lore.kernel.org/r/20241021115620.1616617-7-quic_mdalam%40quicinc.com
patch subject: [PATCH v12 6/8] spi: spi-qpic: add driver for QCOM SPI NAND flash Interface
config: sparc64-randconfig-r073-20241023 (https://download.01.org/0day-ci/archive/20241025/202410252355.ZofaMeku-lkp@intel.com/config)
compiler: sparc64-linux-gcc (GCC) 14.1.0

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp at intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202410252355.ZofaMeku-lkp@intel.com/

smatch warnings:
drivers/spi/spi-qpic-snand.c:1260 qcom_spi_write_page() warn: unsigned 'cmd' is never less than zero.
drivers/spi/spi-qpic-snand.c:1279 qcom_spi_send_cmdaddr() warn: unsigned 'cmd' is never less than zero.

vim +/cmd +1260 drivers/spi/spi-qpic-snand.c

  1252	
  1253	static int qcom_spi_write_page(struct qcom_nand_controller *snandc,
  1254				       const struct spi_mem_op *op)
  1255	{
  1256		struct qpic_snand_op s_op = {};
  1257		u32 cmd;
  1258	
  1259		cmd = qcom_spi_cmd_mapping(snandc, op->cmd.opcode);
> 1260		if (cmd < 0)
  1261			return cmd;
  1262	
  1263		s_op.cmd_reg = cmd;
  1264	
  1265		if (op->cmd.opcode == SPINAND_PROGRAM_LOAD)
  1266			snandc->qspi->data_buf = (u8 *)op->data.buf.out;
  1267	
  1268		return 0;
  1269	}
  1270	
  1271	static int qcom_spi_send_cmdaddr(struct qcom_nand_controller *snandc,
  1272					 const struct spi_mem_op *op)
  1273	{
  1274		struct qpic_snand_op s_op = {};
  1275		u32 cmd;
  1276		int ret, opcode;
  1277	
  1278		cmd = qcom_spi_cmd_mapping(snandc, op->cmd.opcode);
> 1279		if (cmd < 0)
  1280			return cmd;
  1281	
  1282		s_op.cmd_reg = cmd;
  1283		s_op.addr1_reg = op->addr.val;
  1284		s_op.addr2_reg = 0;
  1285	
  1286		opcode = op->cmd.opcode;
  1287	
  1288		switch (opcode) {
  1289		case SPINAND_WRITE_EN:
  1290			return 0;
  1291		case SPINAND_PROGRAM_EXECUTE:
  1292			s_op.addr1_reg = op->addr.val << 16;
  1293			s_op.addr2_reg = op->addr.val >> 16 & 0xff;
  1294			snandc->qspi->addr1 = cpu_to_le32(s_op.addr1_reg);
  1295			snandc->qspi->addr2 = cpu_to_le32(s_op.addr2_reg);
  1296			snandc->qspi->cmd = cpu_to_le32(cmd);
  1297			return qcom_spi_program_execute(snandc, op);
  1298		case SPINAND_READ:
  1299			s_op.addr1_reg = (op->addr.val << 16);
  1300			s_op.addr2_reg = op->addr.val >> 16 & 0xff;
  1301			snandc->qspi->addr1 = cpu_to_le32(s_op.addr1_reg);
  1302			snandc->qspi->addr2 = cpu_to_le32(s_op.addr2_reg);
  1303			snandc->qspi->cmd = cpu_to_le32(cmd);
  1304			return 0;
  1305		case SPINAND_ERASE:
  1306			s_op.addr2_reg = (op->addr.val >> 16) & 0xffff;
  1307			s_op.addr1_reg = op->addr.val;
  1308			snandc->qspi->addr1 = cpu_to_le32(s_op.addr1_reg << 16);
  1309			snandc->qspi->addr2 = cpu_to_le32(s_op.addr2_reg);
  1310			snandc->qspi->cmd = cpu_to_le32(cmd);
  1311			qcom_spi_block_erase(snandc);
  1312			return 0;
  1313		default:
  1314			break;
  1315		}
  1316	
  1317		snandc->buf_count = 0;
  1318		snandc->buf_start = 0;
  1319		qcom_clear_read_regs(snandc);
  1320		qcom_clear_bam_transaction(snandc);
  1321	
  1322		snandc->regs->cmd = cpu_to_le32(s_op.cmd_reg);
  1323		snandc->regs->exec = cpu_to_le32(1);
  1324		snandc->regs->addr0 = cpu_to_le32(s_op.addr1_reg);
  1325		snandc->regs->addr1 = cpu_to_le32(s_op.addr2_reg);
  1326	
  1327		qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 3, NAND_BAM_NEXT_SGL);
  1328		qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
  1329	
  1330		ret = qcom_submit_descs(snandc);
  1331		if (ret)
  1332			dev_err(snandc->dev, "failure in submitting cmd descriptor\n");
  1333	
  1334		return ret;
  1335	}
  1336	

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