[PATCH] mtd: spi-nor: core: replace dummy buswidth from addr to data

[Tudor Ambarus]

On 11/12/24 6:45 AM, Tudor Ambarus wrote:
> 
> 
> On 11/12/24 2:42 AM, Cheng Ming Lin wrote:
>> Hi Tudor,
>>
>> Tudor Ambarus <tudor.ambarus at linaro.org> 於 2024年11月11日 週一 下午6:18寫道：
>>>
>>>
>>>
>>> On 11/7/24 9:30 AM, Cheng Ming Lin wrote:
>>>> From: Cheng Ming Lin <chengminglin at mxic.com.tw>
>>>>
>>>> The default dummy cycle for Macronix SPI NOR flash in Octal Output
>>>> Read Mode(1-1-8) is 20.
>>>>
>>>> Currently, the dummy buswidth is set according to the address bus width.
>>>> In the 1-1-8 mode, this means the dummy buswidth is 1. When converting
>>>> dummy cycles to bytes, this results in 20 x 1 / 8 = 2 bytes, causing the
>>>> host to read data 4 cycles too early.
>>>>
>>>> Since the protocol data buswidth is always greater than or equal to the
>>>> address buswidth. Setting the dummy buswidth to match the data buswidth
>>>> increases the likelihood that the dummy cycle-to-byte conversion will be
>>>> divisible, preventing the host from reading data prematurely.
>>>
>>> This is still very wrong and the `fix` is working just by chance.
>>> Consider what happens when one requires 10 dummy cycles. BTW, does this
>>> fix a real problem, or it's just a theoretical fix?
>>
>> In 1-1-8 mode, setting the dummy buswidth to match the data
>> buswidth ensures a dummy buswidth of 8, which can accommodate
>> all types of dummy cycles.
>>
>> This patch resolves a significant issue in 1-1-8 mode, as described above.
>>
> 
> shall we add a fixes tag then, and a cc to stable?

I need a patch today if you want it integrated in the SPI NOR PR.
Otherwise we'll queue one in the -rc phase.