[PATCH v6 2/2] dt-bindings: mtd: davinci: convert to yaml

[Krzysztof Kozlowski]

On Thu, Nov 07, 2024 at 10:19:54AM +0100, Marcus Folkesson wrote:
> Convert the bindings to yaml format.
> 
> Signed-off-by: Marcus Folkesson <marcus.folkesson at gmail.com>
> ---
>  .../devicetree/bindings/mtd/davinci-nand.txt       |  94 ---------------
>  .../devicetree/bindings/mtd/ti,davinci-nand.yaml   | 134 +++++++++++++++++++++
>  2 files changed, 134 insertions(+), 94 deletions(-)

...

> +allOf:
> +  - $ref: nand-controller.yaml
> +
> +properties:
> +  compatible:
> +    enum:
> +      - ti,davinci-nand
> +      - ti,keystone-nand
> +
> +  reg:
> +    items:
> +      - description:
> +          Access window.

Merge two lines. See other files how they do it.

> +      - description:
> +          AEMIF control registers

Merge two lines

> +
> +  "#address-cells":
> +    const: 1
> +
> +  "#size-cells":
> +    const: 0

These two properties are not needed, drop. I don't understand why did
they appear here. Changelog also does no explain it.

> +
> +  partitions:
> +    $ref: /schemas/mtd/partitions/partitions.yaml
> +
> +  ti,davinci-chipselect:
> +    description:
> +      Number of chipselect. Indicate on the davinci_nand driver which
> +      chipselect is used for accessing the nand.
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    enum: [0, 1, 2, 3]
> +
> +  ti,davinci-mask-ale:
> +    description:
> +      Mask for ALE. Needed for executing address phase. These offset will be
> +      added to the base address for the chip select space the NAND Flash
> +      device is connected to.
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    default: 0x08
> +
> +  ti,davinci-mask-cle:
> +    description:
> +      Mask for CLE. Needed for executing command phase. These offset will be
> +      added to the base address for the chip select space the NAND Flash device
> +      is connected to.
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    default: 0x10
> +
> +  ti,davinci-mask-chipsel:
> +    description:
> +      Mask for chipselect address. Needed to mask addresses for given
> +      chipselect.
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    default: 0
> +
> +  ti,davinci-ecc-bits:
> +    description: Used ECC bits.
> +    enum: [1, 4]
> +
> +  ti,davinci-ecc-mode:
> +    description: Operation mode of the NAND ECC mode.
> +    $ref: /schemas/types.yaml#/definitions/string
> +    enum: [none, soft, hw, on-die]
> +    deprecated: true
> +
> +  ti,davinci-nand-buswidth:
> +    description: Bus width to the NAND chip
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    enum: [8, 16]
> +    default: 8
> +    deprecated: true
> +
> +  ti,davinci-nand-use-bbt:
> +    type: boolean
> +    description:
> +      Use flash based bad block table support. OOB identifier is saved in OOB
> +      area.
> +    deprecated: true
> +
> +required:
> +  - compatible
> +  - reg
> +  - "#address-cells"
> +  - "#size-cells"

Drop these two.

> +  - ti,davinci-chipselect
> +
> +unevaluatedProperties: false
> +
> +examples:
> +  - |
> +    bus {
> +      #address-cells = <2>;
> +      #size-cells = <1>;
> +
> +      nand-controller at 2000000,0 {
> +        compatible = "ti,davinci-nand";
> +        #address-cells = <1>;
> +        #size-cells = <0>;
> +        reg = <0 0x02000000 0x02000000
> +        1 0x00000000 0x00008000>;

Two items must be encoded as two items, so two <> <>
Also messed alignment. See DTS coding style.

> +
> +        ti,davinci-chipselect = <1>;
> +        ti,davinci-mask-ale = <0>;
> +        ti,davinci-mask-cle = <0>;
> +        ti,davinci-mask-chipsel = <0>;
> +
> +        ti,davinci-nand-buswidth = <16>;
> +        ti,davinci-ecc-mode = "hw";
> +        ti,davinci-ecc-bits = <4>;
> +        ti,davinci-nand-use-bbt;
> +
> +        partitions {

Where are the partitions documented? In which binding? Don't you miss
mtd.yaml? I think this binding misses some references, but I am not sure
which ones.

Best regards,
Krzysztof