[PATCH v14 7/8] arm64: dts: qcom: ipq9574: Add SPI nand support

[Md Sadre Alam]

On 12/5/2024 10:49 PM, Konrad Dybcio wrote:
> On 20.11.2024 10:15 AM, Md Sadre Alam wrote:
>> Add SPI NAND support for ipq9574 SoC.
>>
>> Signed-off-by: Md Sadre Alam <quic_mdalam at quicinc.com>
>> ---
> 
> [...]
> 
> Feel free to put dt patches in a separate series after Miquel picks
> up the mtd changes
Ok
> 
>>   &usb_0_dwc3 {
>> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> index d1fd35ebc4a2..45fb26bc9480 100644
> 
> board and dtsi patches should be 2 separate ones
Ok
> 
>> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> @@ -330,6 +330,33 @@ tcsr: syscon at 1937000 {
>>   			reg = <0x01937000 0x21000>;
>>   		};
>>   
>> +		qpic_bam: dma-controller at 7984000 {
>> +			compatible = "qcom,bam-v1.7.0";
>> +			reg = <0x7984000 0x1c000>;
> 
> Please pad the address part to 8 hex digits with leading zeroes
Ok
> 
>> +			interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
>> +			clocks = <&gcc GCC_QPIC_AHB_CLK>;
>> +			clock-names = "bam_clk";
>> +			#dma-cells = <1>;
>> +			qcom,ee = <0>;
>> +			status = "disabled";
>> +		};
>> +
>> +		qpic_nand: spi at 79b0000 {
>> +			compatible = "qcom,ipq9574-snand";
>> +			reg = <0x79b0000 0x10000>;
>> +			#address-cells = <1>;
>> +			#size-cells = <0>;
>> +			clocks = <&gcc GCC_QPIC_CLK>,
>> +				 <&gcc GCC_QPIC_AHB_CLK>,
>> +				 <&gcc GCC_QPIC_IO_MACRO_CLK>;
>> +			clock-names = "core", "aon", "iom";
>> +			dmas = <&qpic_bam 0>,
>> +			       <&qpic_bam 1>,
>> +			       <&qpic_bam 2>;
>> +			dma-names = "tx", "rx", "cmd";
> 
> Please make clock/dma names a vertical list, like clocks/dmas
Ok
> 
> Also, is it okay not to use any of the GCC_QPIC_BCR/
> GCC_QPIC_AHB_ARES/GCC_QPIC_ARES resets found in GCC?
It's recommended by HW team, will check once again with HW
team.
> 
> Konrad