[PATCH v2] mtd: spi-nor: add support for MRAM Everspin EM008LX

[Claus Fabig]

The Everspin EM008LX MRAM has 8Mb and is populated on a custom board
using Microchip's PCI12000 spi host controller running on low 30MHz clock.
According to Everspin Read Fast (0xb) command below 60MHz is neither
specified and nor tested. Test shows that using Read Fast (0xb) will
result in reading inconsistent data in this setup but writing is fine, so
only supporting Read (0x3) command should be acceptable for the moment.
The device is JEDEC compatible (JESD251 and JESD251-1) but not able to
provide SFDP information.

For spec v3.2 refer to Link: https://www.everspin.com/file/158315/download.

Successfully tested according to
Link: https://www.kernel.org/doc/html/latest/driver-api/mtd/spi-nor.html.

Signed-off-by: Claus Fabig <claus.fabig at emerson.com>
---
Changes in V2:
 - add id for probing instead of name
 - change sector size from 1MB to 64k

test em008lxb MRAM
cat /sys/bus/spi/devices/spi-EMR5555\:00/spi-nor/partname
em008lx
cat /sys/bus/spi/devices/spi-EMR5555\:00/spi-nor/jedec_id
6bbb14
cat /sys/bus/spi/devices/spi-EMR5555\:00/spi-nor/manufacturer
everspin
cat /sys/kernel/debug/spi-nor/spi-EMR5555\:00/capabilities
Supported read modes by the flash
 1S-1S-1S
  opcode	0x03
  mode cycles	0
  dummy cycles	0

Supported page program modes by the flash
 1S-1S-1S
  opcode	0x02
cat /sys/kernel/debug/spi-nor/spi-EMR5555\:00/params
name		em008lx
id		6b bb 14 10 48 5f
size		1.00 MiB
write size	1
page size	256
address nbytes	3
flags		HAS_SR_TB | HAS_16BIT_SR | HAS_4BIT_BP | HAS_SR_BP3_BIT6

opcodes
 read		0x03
  dummy cycles	0
 erase		0xd8
 program	0x02
 8D extension	none

protocols
 read		1S-1S-1S
 write		1S-1S-1S
 register	1S-1S-1S

erase commands
 d8 (64.0 KiB) [0]
 c7 (1.00 MiB)

sector map
 region (in hex)   | erase mask | overlaid
 ------------------+------------+----------
 00000000-000fffff |     [0   ] | no
cat /proc/mtd
dev:    size   erasesize  name
mtd0: 00020000 00020000 "spi-EMR1010:00"
mtd1: 00100000 00010000 "spi-EMR5555:00"
mtd_debug info /dev/mtd1
mtd.type = MTD_NORFLASH
mtd.flags = MTD_CAP_NORFLASH
mtd.size = 1048576 (1M)
mtd.erasesize = 65536 (64K)
mtd.writesize = 1 
mtd.oobsize = 0 
regions = 0

dd if=/dev/urandom of=spi_test bs=1M count=1
mtd_debug erase /dev/mtd1 0 1048576
mtd_debug read /dev/mtd1 0 1048576 spi_read
Copied 1048576 bytes from address 0x00000000 in flash to spi_read
hexdump spi_read
0000000 ffff ffff ffff ffff ffff ffff ffff ffff
*
0100000
sha256sum spi_read
f5fb04aa5b882706b9309e885f19477261336ef76a150c3b4d3489dfac3953ec  spi_read
mtd_debug write /dev/mtd1 0 1048576 spi_test
Copied 1048576 bytes from spi_test to address 0x00000000 in flash
mtd_debug read /dev/mtd1 0 1048576 spi_read
Copied 1048576 bytes from address 0x00000000 in flash to spi_read
sha256sum spi*
8b73cb3cf9a032236fc3f41c974fced7b8dd43262628c5425f178c84ad619965  spi_read
8b73cb3cf9a032236fc3f41c974fced7b8dd43262628c5425f178c84ad619965  spi_test

 drivers/mtd/spi-nor/everspin.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/mtd/spi-nor/everspin.c b/drivers/mtd/spi-nor/everspin.c
index add37104d673..178529ed0a28 100644
--- a/drivers/mtd/spi-nor/everspin.c
+++ b/drivers/mtd/spi-nor/everspin.c
@@ -31,6 +31,12 @@ static const struct flash_info everspin_nor_parts[] = {
 		.size = SZ_512K,
 		.sector_size = SZ_512K,
 		.flags = SPI_NOR_NO_ERASE,
+	}, {
+		.id = SNOR_ID(0x6b, 0xbb, 0x14),
+		.name = "em008lx",
+		.size = SZ_1M,
+		.sector_size = SZ_64K,
+		.flags = SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP | SPI_NOR_BP3_SR_BIT6,
 	}
 };
 
-- 
2.43.0