[PATCH v4 5/6] mtd: spi-nor: core: Allow specifying the byte order in DTR mode

[Tudor Ambarus]

Hi, Jaime,

On 08.09.2023 09:43, Jaime Liao wrote:
> From: JaimeLiao <jaimeliao at mxic.com.tw>
> 
> Macronix swaps bytes on a 16-bit boundary when configured in Octal DTR.
> The byte order of 16-bit words is swapped when read or written in 8D-8D-8D
> mode compared to STR modes. Allow operations to specify the byte order in
> DTR mode, so that controllers can swap the bytes back at run-time to
> address the flash's endianness requirements, if they are capable. If the
> controllers are not capable of swapping the bytes, the protocol is
> downgrade via spi_nor_spimem_adjust_hwcaps(). When available, the swapping
> of the bytes is always done regardless if it's a data or register access,
> so that we comply with the JESD216 requirements: "Byte order of 16-bit
> words is swapped when read in 8D-8D-8D mode compared to 1-1-1".
> 

There's a bit in SFDP that specifies whether the flash swaps the bytes
or not in 8d-8d-8d mode. See BFPT DWORD[18] bit 31. Can we query the
SFDP instead of introducing a new info flag?

Cheers,
ta