[PATCH v4 4/6] spi: spi-mem: Allow specifying the byte order in DTR mode

[Tudor Ambarus]

On 08.09.2023 09:43, Jaime Liao wrote:
> From: JaimeLiao <jaimeliao at mxic.com.tw>
> 
> There are NOR flashes (Macronix) that swap the bytes on a 16-bit
> boundary when configured in Octal DTR mode. The byte order of
> 16-bit words is swapped when read or written in Octal Double
> Transfer Rate (DTR) mode compared to Single Transfer Rate (STR)
> modes. If one writes D0 D1 D2 D3 bytes using 1-1-1 mode, and uses
> 8D-8D-8D SPI mode for reading, it will read back D1 D0 D3 D2.
> Swapping the bytes may introduce some endianness problems. It can
> affect the boot sequence if the entire boot sequence is not handled
> in either 8D-8D-8D mode or 1-1-1 mode. So we must swap the bytes
> back to have the same byte order as in STR modes. Fortunately there
> are controllers that could swap the bytes back at runtime,
> addressing the flash's endiannesses requirements. Provide a way for
> the upper layers to specify the byte order in Octal DTR mode.
> 

Jaime,

would you please remind me how this works? Does these flashes always
swap the bytes? Is there a flash configuration register where you can
specify whether to swap the bytes or not?

If it's not configurable I'm thinking of introducing a hook that allows
flashes to program the spi controller to swap the bytes and if the spi
controller does not support byte swapping, to just return an error and
fallback to 8-8-8/1-1-1 mode. We can't break the bootchain.

Cheers,
ta