[PATCH] mtd: spi-nor: micron-st: Add support for mt25qu01g

[Michael Walle]

Am 25. Oktober 2023 20:35:40 OESZ schrieb Fabio Estevam <festevam at gmail.com>:
>Hi Tudor,
>
>On Wed, Oct 25, 2023 at 8:56 AM Fabio Estevam <festevam at gmail.com> wrote:
>
>> In the meantime, could you please consider the v2 proposal?
>> https://lore.kernel.org/linux-mtd/20231024135826.2729088-1-festevam@gmail.com/T/#u
>>
>> mt25qu01g is very similar to the already supported mt25qu02g.
>>
>> In v2, the .size and .no_sfdp_flag fields were removed, which is an
>> improvement over mt25qu02g.
>>
>> Only NO_CHIP_ERASE still needs to be passed, but that can be removed
>> later when the
>> mt25qu01g_post_sfdp_fixup() is implemented.
>>
>> Does this sound reasonable?
>
>I have also tried adding a mt25qu01g_post_sfdp_fixup().
>
>The changes below should be split into 3 different patches, but just
>wanted to share them with you for feedback.

Two patches. no? one for the no chip erase flag and one for adding the flash. 

And I'd prefer this version. 

>diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
>index 1c443fe568cf..f85ea57534ba 100644
>--- a/drivers/mtd/spi-nor/core.c
>+++ b/drivers/mtd/spi-nor/core.c
>@@ -2850,7 +2850,7 @@ static void spi_nor_init_flags(struct spi_nor *nor)
>                        nor->flags |= SNOR_F_HAS_SR_BP3_BIT6;
>        }
>
>-       if (flags & NO_CHIP_ERASE)
>+       if (flags & NO_CHIP_ERASE || nor->params->n_dice > 1)
>                nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
>
>        if (flags & SPI_NOR_RWW && nor->params->n_banks > 1 &&
>diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c
>index 8920547c12bf..21fef439d5f1 100644
>--- a/drivers/mtd/spi-nor/micron-st.c
>+++ b/drivers/mtd/spi-nor/micron-st.c
>@@ -192,6 +192,20 @@ static struct spi_nor_fixups mt25qu512a_fixups = {
>        .post_bfpt = mt25qu512a_post_bfpt_fixup,
> };
>
>+static int mt25qu01g_post_sfdp_fixup(struct spi_nor *nor)
>+{
>+       struct spi_nor_flash_parameter *params = nor->params;
>+
>+       /* MT25QU01G does not define the SCCR entry, so pass n_dice
>manually.  */
>+       params->n_dice = 2;
>+
>+       return 0;
>+}
>+
>+static struct spi_nor_fixups mt25qu01g_fixups = {
>+       .post_sfdp = mt25qu01g_post_sfdp_fixup,
>+};
>+
> static const struct flash_info st_nor_parts[] = {
>        {
>                .name = "m25p05-nonjedec",
>@@ -429,6 +443,11 @@ static const struct flash_info st_nor_parts[] = {
>                         SPI_NOR_BP3_SR_BIT6,
>                .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,
>                .mfr_flags = USE_FSR,
>+       }, {
>+               .id = SNOR_ID(0x20, 0xbb, 0x21, 0x10, 0x44, 0x00),
>+               .name = "mt25qu01g",
>+               .mfr_flags = USE_FSR,

out of curiosity. does it also work without USE_FSR? I'm not implying to remove it, just want to get a feeling if this 
needed at all. 

-michael

>+               .fixups = &mt25qu01g_fixups
>        }, {
>                .id = SNOR_ID(0x20, 0xbb, 0x21),
>                .name = "n25q00a",
>
>Please let me know what is your preference.
>
>Thanks