[PATCH v3 3/3] mtd: micron-st: add post bfpt fix for mt25qu512a

[Mamta Shukla]

Parsing SFDP Table for mt25qu512a adds flag for 16Bit Status Register.

 cat /sys/kernel/debug/spi-nor/spi-PRP0001:00/params
 name            mt25qu512a
 id              20 bb 20 10 44 00
 size            64.0 MiB
 write size      1
 page size       256
 address nbytes  4
 flags           HAS_SR_TB | 4B_OPCODES | HAS_4BAIT | HAS_LOCK | HAS_16BIT_SR |
  HAS_4BIT_BP | HAS_SR_BP3_BIT6 | SOFT_RESET

This Flag leads to miscalculation of BP bits and thus causes failure of lock/
unlock functionality of chip. Hence, add post bfpt fixups to fix parsed
sfdp setting.

Signed-off-by: Mamta Shukla <mamta.shukla at leica-geosystems.com>
Signed-off-by: Tudor Ambarus <tudor.ambarus at linaro.org>
---
 drivers/mtd/spi-nor/micron-st.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c
index 4feb03ee2d13..b7bf0570c01f 100644
--- a/drivers/mtd/spi-nor/micron-st.c
+++ b/drivers/mtd/spi-nor/micron-st.c
@@ -180,6 +180,19 @@ static const struct flash_info micron_nor_parts[] = {
 	},
 };
 
+
+static int mt25qu512a_post_bfpt_fixup(struct spi_nor *nor,
+								const struct sfdp_parameter_header *bfpt_header,
+								const struct sfdp_bfpt *bfpt)
+{
+	nor->flags &= ~SNOR_F_HAS_16BIT_SR;
+	return 0;
+}
+
+static struct spi_nor_fixups mt25qu512a_fixups = {
+	.post_bfpt = mt25qu512a_post_bfpt_fixup,
+};
+
 static const struct flash_info st_nor_parts[] = {
 	{
 		.name = "m25p05-nonjedec",
@@ -408,6 +421,7 @@ static const struct flash_info st_nor_parts[] = {
 		.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
 			SPI_NOR_BP3_SR_BIT6,
 		.mfr_flags = USE_FSR,
+		.fixups = &mt25qu512a_fixups,
 	}, {
 		.id = SNOR_ID(0x20, 0xbb, 0x20),
 		.name = "n25q512a",
-- 
2.34.1