[PATCH v6 5/7] spi: mxic: Add support for swapping byte

[liao jaime]

Hi Michael


>
> Hi Jaime,
>
> > Some SPI-NOR flash swap the bytes on a 16-bit boundary when
> > configured in Octal DTR mode. It means data format D0 D1 D2 D3
> > would be swapped to D1 D0 D3 D2. So that whether controller
> > support swapping bytes should be checked before enable Octal
> > DTR mode. Add swap byte support on a 16-bit boundary when
> > configured in Octal DTR mode for Macronix xSPI host controller
> > dirver.
> >
> > Signed-off-by: JaimeLiao <jaimeliao at mxic.com.tw>
> > ---
> >  drivers/spi/spi-mxic.c | 1 +
> >  1 file changed, 1 insertion(+)
> >
> > diff --git a/drivers/spi/spi-mxic.c b/drivers/spi/spi-mxic.c
> > index 60c9f3048ac9..085c9037d6f5 100644
> > --- a/drivers/spi/spi-mxic.c
> > +++ b/drivers/spi/spi-mxic.c
> > @@ -572,6 +572,7 @@ static const struct spi_controller_mem_ops
> > mxic_spi_mem_ops = {
> >
> >  static const struct spi_controller_mem_caps mxic_spi_mem_caps = {
> >       .dtr = true,
> > +     .dtr_swab16 = true,
> >       .ecc = true,
> >  };
>
> I'm confused. How can this swap the bytes depending on the flashes
> requirements? I.e. the controller should look at the spi-mem operation
> and either swap the bytes or it should leave them as is.
Byte order in 8D-8D-8D mode could get by parsing BFPT 18th Dword 31th bit.
I think flash driver should notify controller driver and verify whether the
controller driver support byte swap functionality. If flash requires byte swap
in octal DTR mode but the controller driver doesn't support it, then octal DTR
should not be enabled. The controller driver should indicate in the
description of
"spi_controller_mem_caps" whether this feature is supported. The implementation
of this feature should be handled separately by each controller drive
since the design
may vary for each one.

>
> -michael
>

Thanks
Jaime