[PATCH v5 2/6] spi: spi-mem: Allow specifying the byte order in DTR mode

[liao jaime]

Hi

>
>
>
> On 11/17/23 08:38, Jaime Liao wrote:
> > From: JaimeLiao <jaimeliao at mxic.com.tw>
> >
> > There are NOR flashes (Macronix) that swap the bytes on a 16-bit
> > boundary when configured in Octal DTR mode. The byte order of
> > 16-bit words is swapped when read or written in Octal Double
> > Transfer Rate (DTR) mode compared to Single Transfer Rate (STR)
> > modes. If one writes D0 D1 D2 D3 bytes using 1-1-1 mode, and uses
> > 8D-8D-8D SPI mode for reading, it will read back D1 D0 D3 D2.
> > Swapping the bytes may introduce some endianness problems. It can
> > affect the boot sequence if the entire boot sequence is not handled
> > in either 8D-8D-8D mode or 1-1-1 mode. So we must swap the bytes
> > back to have the same byte order as in STR modes. Fortunately there
> > are controllers that could swap the bytes back at runtime,
> > addressing the flash's endiannesses requirements. Provide a way for
> > the upper layers to specify the byte order in Octal DTR mode.
> >
> > Merge Tudor's patch and add modifications for suiting newer version
> > of Linux kernel.
> >
> > Signed-off-by: Tudor Ambarus <tudor.ambarus at linaro.org>
> > Signed-off-by: JaimeLiao <jaimeliao at mxic.com.tw>
> > ---
> >  drivers/spi/spi-mem.c       | 4 ++++
> >  include/linux/spi/spi-mem.h | 6 ++++++
> >  2 files changed, 10 insertions(+)
> >
> > diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
> > index edd7430d4c05..9c03b5617fff 100644
> > --- a/drivers/spi/spi-mem.c
> > +++ b/drivers/spi/spi-mem.c
> > @@ -172,6 +172,10 @@ bool spi_mem_default_supports_op(struct spi_mem *mem,
> >               if (!spi_mem_controller_is_capable(ctlr, dtr))
> >                       return false;
> >
> > +             if (op->data.dtr_swab16 &&
> > +                 !(spi_mem_controller_is_capable(ctlr, dtr_swab16)))
> > +                     return false;
> > +
>
> so if the controller supports swapping back the bytes, then 8d-8d-8d
> will be supported, otherwise not. Shall the swap back be user configurable?
Yes, I validate it on macronix spi controller driver.
8d-8d-8d mode will not support if controller driver didn't support
swapping bytes.

Thanks
Jaime