[PATCH RFC 0/4] Add set_iofv() callback

[Biju Das]

Hi Michael Walle,

> Subject: RE: [PATCH RFC 0/4] Add set_iofv() callback
> 
> Hi Michael Walle,
> 
> > Subject: RE: [PATCH RFC 0/4] Add set_iofv() callback
> >
> 
> >
> > > Subject: Re: [PATCH RFC 0/4] Add set_iofv() callback
> > >
> > > Hi Biju,
> > >
> > > >> >> Thus I was saying, that we probably wont support that and the
> > > >> >> easiest fix should be to disable this behavior for the atmel
> > > >> >> flash (there was nv setting).
> > > >> >
> > > >> > The fix up is invoked only for quad mode, I believe it is safe
> > > >> > to add fixup for micron flash As it is the one deviating from
> > > >> > normal according to you, rather than adding fixup for generic
> > > >> > flash like ATMEL flash(Now Renesas flash)
> > > >>
> > > >> Could you please try setting bit 4 in the Nonvolatile
> > > >> Configuration Register (Table 7) and see if the problem goes away?
> > > >
> > > > You mean, if it works, we need to disable reset for all the
> > > > boards, maybe at bootloader level??
> > >
> > > Not necessarily. First, just to confirm that it is actually the
> > > reset circuit. You can also compare the part numbers of the flash.
> > > There is a flash with IO3/RESET# and IO3/HOLD# (and a flash with a
> > > dedicated reset pin).
> >
> > Part is MT25QU512ABB8E12-0SIT, As per the schematic, flash has a
> > dedicated RESET# with 10K pullup connected to SoC QSPI_RESET pin.
> >
> > DQ0, DQ1, W#/DQ2 and DQ3 lines on the flash are connected without any
> > pullups to the SoC QSPI0_{0..3} pins.
> >
> > >
> > > If that's the case, it looks like a hardware bug on your board. You
> > > left the reset pin floating. So you'd also not be able to boot from
> > > the NOR flash, right?
> >
> > I am booting from NOR flash. BootRom code reads SPI flash and executes
> > BL2.
> > BL2 loads BL33 and U-boot from NOR flash. If this is the case, do you
> > think it is a Hw bug on the board?
> >
> > >
> > > > OK, I will check that. Currently I have read that register and it
> > > > is showing a value Of 0xffbb. I need to do write operation. Before
> > > > that how do we recover flash, if something goes wrong during
> > > > writing for NV register?
> > >
> > > You should always be able to write that register from the bootloader.
> > > Maybe also through raw commands (like sspi in uboot).
> >
> > Thanks for the pointer, I haven't explored the uboot path.
> 
> I have disabled RESET# bit in the Nonvolatile Configuration Register
> (Table 7) and borad doesn't boot any more.
> 
> By default that bit is set.
> 
> [    2.530291] ###### Before write Read cmd=b5 val=ff
> [    2.530431] ###### write cmd=b1 val=ef
> [    2.535518] ###### Read cmd=b5 val=ef
> 
> 
> NOTICE:  BL2: Built : 14:59:28, Nov 10 2023
> ERROR:   BL2: Failed to load image id 3 (-2)
> NOTICE:  BL2: v2.9(release):v2.5/rzg2l-1.00-3883-gc314a391c
> NOTICE:  BL2: Built : 14:59:28, Nov 10 2023
> ERROR:   BL2: Failed to load image id 3 (-2)
> NOTICE:  BL2: v2.9(release):v2.5/rzg2l-1.00-3883-gc314a391c
> 
> What is your thoughts on this? How do we proceed now?
> 

Just to add I have recovered the spi flash by booting with eMMC boot and
Setting bit4 in Table 7. Now I can boot with SPI flash.

[    2.521879] ###### Before write Read cmd=b5 val=ef
[    2.522163] ###### write cmd=b1 val=ff
[    2.527350] ###### Read cmd=b5 val=ff

How do we proceed now? Krysztof/Geert, what is your thoughts?

Shall we set default values as Hi-Z for IO FV in bus driver and

As Micron flash is behaving differently shall we use SoC register(IOFV) to fix the
4-bit tx mode like patch [1] or you prefer [2]? 

[1]
https://patchwork.kernel.org/project/linux-renesas-soc/patch/20230830145835.296690-1-biju.das.jz@bp.renesas.com/


[2]
https://lore.kernel.org/linux-renesas-soc/dcfa2cab21fc85bb9b2b0c1ceb754a1a@walle.cc/T/#t


Please find the sample code for setting NV Config register for micron flash

+#define MICRON_ST_RD_NV_OP(buf)                                                \
+       SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDNV, 0),                   \
+                  SPI_MEM_OP_NO_ADDR,                                  \
+                  SPI_MEM_OP_NO_DUMMY,                                 \
+                  SPI_MEM_OP_DATA_IN(2, buf, 0))
+
+#define MICRON_ST_WR_NV_OP(naddr, addr, ndata, buf)            \
+       SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRNV, 0),           \
+                  SPI_MEM_OP_NO_ADDR,                  \
+                  SPI_MEM_OP_NO_DUMMY,                                 \
+                  SPI_MEM_OP_DATA_OUT(2, buf, 0))
+
+#define SPINOR_OP_RDNV         0xb5    /* Read flag status register */
+#define SPINOR_OP_WRNV         0xb1    /* Write flag status register */


int spi_nor_scan(struct spi_nor *nor, const char *name,
                 const struct spi_nor_hwcaps *hwcaps)
 {
@@ -3455,6 +3470,8 @@ int spi_nor_scan(struct spi_nor *nor, const char *name,
        struct mtd_info *mtd = &nor->mtd;
        int ret;
        int i;
+       struct spi_mem_op op;
+
 
        ret = spi_nor_check(nor);
        if (ret)
@@ -3479,6 +3496,23 @@ int spi_nor_scan(struct spi_nor *nor, const char *name,
        if (!nor->bouncebuf)
                return -ENOMEM;
 
+       nor->flags &= ~SNOR_F_HAS_16BIT_SR;
+       op = (struct spi_mem_op) MICRON_ST_RD_NV_OP(nor->bouncebuf);
+       spi_nor_read_any_reg(nor, &op, nor->reg_proto);
+       pr_err("###### Before write Read cmd=%x val=%x",SPINOR_OP_RDNV, nor->bouncebuf[0]);
+
+       nor->bouncebuf[0] = 0xff;
+       nor->bouncebuf[1] = 0xff;
+       op = (struct spi_mem_op)
+               MICRON_ST_WR_NV_OP(0, SPINOR_OP_WRNV, 2, nor->bouncebuf);
+       ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto);
+
+       pr_err("###### write cmd=%x val=%x", SPINOR_OP_WRNV, nor->bouncebuf[0]);
+
+       op = (struct spi_mem_op) MICRON_ST_RD_NV_OP(nor->bouncebuf);
+       spi_nor_read_any_reg(nor, &op, nor->reg_proto);
+       pr_err("###### Read cmd=%x val=%x",SPINOR_OP_RDNV, nor->bouncebuf[0]);
+
        ret = spi_nor_hw_reset(nor);
        if (ret)
                return ret;

Cheers,
Biju