[PATCH v1 0/2] Add octal DTR support for Macronix flash

[Tudor Ambarus]

On 7/25/23 10:25, liao jaime wrote:
> Hi Tudor
> 

Hi,

>>
>> On 7/25/23 09:28, Michael Walle wrote:
>>> Am 2023-07-25 10:01, schrieb Tudor Ambarus:
>>>> On 7/25/23 03:23, Jaime Liao wrote:
>>>>> From: JaimeLiao <jaimeliao.tw at gmail.com>
>>>>>
>>>>> This series add method for Macronix Octal DTR Eable/Disable
>>>>> and add Macronix Octal flash support.
>>>>
>>>> Do all these flashes swap the bytes in octal DTR mode? If yes,
>>>> you should add the infrastructure so that controllers can swap
>>>> the bytes back, otherwise you'll break bootloaders which work
>>>> in 1-1-1 mode, and breaking the boot chain is unacceptable.
> No, only parts of flashes.
> MX25UM51345G : flash without swap bytes in octal dtr mode
> MX25UM51245G : flash will swap bytes in octal dtr mode
> So that I hope flashes without swap the bytes can be support.

Flashes that don't swap bytes by default are ok with the current
support that exists in spimem. So please start with these first.

> And I will send new patch for mention flashes which swap the bytes
> in Octal DTR mode.

The flashes that swap bytes by default won't be accepted until we
figure out how to sync the configuration between the flash and the
SPI controller.
> 
>>>
>>> It might also be the SPI controller. Was the zynq SPI controller
>>> used before with octal flashes?
>>>
>>
>> No, it's the macronix flashes that swap the bytes by default. At least
>> the one which I've worked with few years ago. Some controllers can
>> swap the bytes back, but they have to be informed from mtd.
> Yes, it should inform mtd.
> 

mtd shall inform the SPI controller and agree on the configuration.
Maybe some bootloaders can use octal DTR and the swap is not needed
at the controller level, as some bootloaders may handle swapped data.
So it should be a configuration choice and a configuration agreement
between mtd and spi.

Cheers,
ta