[PATCH 1/2] mtd: spi-nor: spansion: Consider reserved bits in CFR5 register

Tudor Ambarus tudor.ambarus at linaro.org
Tue Jan 31 01:00:11 PST 2023

On 10.01.2023 18:47, Tudor Ambarus wrote:
> CFR5[6] is reserved bit and must be always 1. Set it to comply with flash
> requirements. While fixing SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_{EN, DS}
> definition, stop using magic numbers and describe the missing bit fields
> in CFR5 register. This is useful for both readability and future possible
> addition of Octal STR mode support.
> Fixes: c3266af101f2 ("mtd: spi-nor: spansion: add support for Cypress Semper flash")
> Cc:stable at vger.kernel.org
> Reported-by: Takahiro Kuwano<Takahiro.Kuwano at infineon.com>
> Signed-off-by: Tudor Ambarus<tudor.ambarus at linaro.org>
> ---
>   drivers/mtd/spi-nor/spansion.c | 9 +++++++--
>   1 file changed, 7 insertions(+), 2 deletions(-)

both applied, thanks!

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