[PATCH] nand_base: force best_mode to be >= 0

[Hector Palacios]

According to the ONFI specification, bit 0 of 'SDR timing mode support'
(bytes 129-130) "shall be 1". That means the NAND supports at least
timing mode 0.

NAND chip Hynix H27U4G8F2GDA-BI (at least) is reading a 0 on this field
which makes best_mode = -1 and the following loop be skipped. An error
code is returned upstream and the NAND probe fails.

Given that sdr_timing_modes *must* be 1 by specification, force best_mode
to be 1 at least, so that this function doesn't return an error on a NAND
that can work with such timings despite reporting an incorrect ONFI value.

Signed-off-by: Hector Palacios <hector.palacios at digi.com>
---
 drivers/mtd/nand/raw/nand_base.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c
index c3cc66039925..474850e4455c 100644
--- a/drivers/mtd/nand/raw/nand_base.c
+++ b/drivers/mtd/nand/raw/nand_base.c
@@ -947,7 +947,7 @@ int nand_choose_best_sdr_timings(struct nand_chip *chip,
 		/* Fallback to slower modes */
 		best_mode = iface->timings.mode;
 	} else if (chip->parameters.onfi) {
-		best_mode = fls(chip->parameters.onfi->sdr_timing_modes) - 1;
+		best_mode = fls(chip->parameters.onfi->sdr_timing_modes | 1) - 1;
 	}
 
 	for (mode = best_mode; mode >= 0; mode--) {