[PATCH v2 7/8] mtd: spi-nor: spansion: Set params->addr_mode_nbytes = 4 for multi-die parts

[tkuw584924 at gmail.com]

From: Takahiro Kuwano <Takahiro.Kuwano at infineon.com>

The params->addr_mode_nbytes is set to 3 during BFPT parse in case of
BFPT_DWORD1_ADDRESS_BYTES_3_OR_4. Infineon SEMPER multi-chip devices are
in 3- or 4-byte address mode by factory default, depending on model number.
3-byte address mode is for backward compatibility for some SoCs. Since we
cannot access to registers in 2nd die by 3-byte addressing. We assume post
BootRom programs change the address mode to 4 before hand-off.

Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano at infineon.com>
---
 drivers/mtd/spi-nor/spansion.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c
index 45377566ecbd..33b44074f941 100644
--- a/drivers/mtd/spi-nor/spansion.c
+++ b/drivers/mtd/spi-nor/spansion.c
@@ -303,6 +303,18 @@ s25hx_t_post_bfpt_fixup(struct spi_nor *nor,
 	/* Replace Quad Enable with volatile version */
 	nor->params->quad_enable = cypress_nor_quad_enable_volatile;
 
+	/*
+	 * The factory default of address mode in multi-die parts (>128MB) may
+	 * be 3- or 4-byte, depending on model number. Since register address of
+	 * 2nd die is mappeted to 32-bit address space, we cannot access to
+	 * registers in 2nd die in 3-byte mode. 3-byte mode is for backward
+	 * compatibility as some SoCs use 3-byte address in their BootROM. So
+	 * far we assume post BootROM programs change the address mode to 4
+	 * before handing off, rather than calling set_4byte_addr_mode() here.
+	 */
+	if (nor->params->size > SZ_128M)
+		nor->params->addr_mode_nbytes = 4;
+
 	return 0;
 }
 
-- 
2.25.1