[PATCH v11 07/10] mtd: spi-nor: Add stacked memories support in spi-nor

[Mahapatra, Amit Kumar]

Hello Tudor,

> -----Original Message-----
> From: Tudor Ambarus <tudor.ambarus at linaro.org>
> Sent: Friday, December 15, 2023 4:03 PM
> To: Mahapatra, Amit Kumar <amit.kumar-mahapatra at amd.com>;
> broonie at kernel.org; pratyush at kernel.org; miquel.raynal at bootlin.com;
> richard at nod.at; vigneshr at ti.com; sbinding at opensource.cirrus.com;
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> rf at opensource.cirrus.com; perex at perex.cz; tiwai at suse.com
> Cc: linux-spi at vger.kernel.org; linux-kernel at vger.kernel.org; michael at walle.cc;
> linux-mtd at lists.infradead.org; nicolas.ferre at microchip.com;
> alexandre.belloni at bootlin.com; claudiu.beznea at tuxon.dev; Simek, Michal
> <michal.simek at amd.com>; linux-arm-kernel at lists.infradead.org; alsa-
> devel at alsa-project.org; patches at opensource.cirrus.com; linux-
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> amitrkcian2002 at gmail.com
> Subject: Re: [PATCH v11 07/10] mtd: spi-nor: Add stacked memories support
> in spi-nor
> 
> 
> 
> On 12/15/23 10:02, Mahapatra, Amit Kumar wrote:
> > Hello Tudor,
> 
> Hi,
> 
> >
> >> -----Original Message-----
> >> From: Tudor Ambarus <tudor.ambarus at linaro.org>
> >> Sent: Friday, December 15, 2023 1:40 PM
> >> To: Mahapatra, Amit Kumar <amit.kumar-mahapatra at amd.com>;
> >> broonie at kernel.org; pratyush at kernel.org; miquel.raynal at bootlin.com;
> >> richard at nod.at; vigneshr at ti.com; sbinding at opensource.cirrus.com;
> >> lee at kernel.org; james.schulman at cirrus.com; david.rhodes at cirrus.com;
> >> rf at opensource.cirrus.com; perex at perex.cz; tiwai at suse.com
> >> Cc: linux-spi at vger.kernel.org; linux-kernel at vger.kernel.org;
> >> michael at walle.cc; linux-mtd at lists.infradead.org;
> >> nicolas.ferre at microchip.com; alexandre.belloni at bootlin.com;
> >> claudiu.beznea at tuxon.dev; Simek, Michal <michal.simek at amd.com>;
> >> linux- arm-kernel at lists.infradead.org; alsa-devel at alsa-project.org;
> >> patches at opensource.cirrus.com; linux-sound at vger.kernel.org; git (AMD-
> >> Xilinx) <git at amd.com>; amitrkcian2002 at gmail.com
> >> Subject: Re: [PATCH v11 07/10] mtd: spi-nor: Add stacked memories
> >> support in spi-nor
> >>
> >>
> >>
> >> On 15.12.2023 09:55, Mahapatra, Amit Kumar wrote:
> >>>> Thanks! Can you share with us what flashes you used for testing in
> >>>> the stacked and parallel configurations?
> >>> I used SPI-NOR QSPI flashes for testing stacked and parallel.
> >>
> >> I got that, I wanted the flash name or device ID.
> >
> > N25Q00A, MX66U2G45G, IS25LP01G & W25H02JV are some of the QSPI
> flashes
> > on which we tested. Additionally, we conducted tests on over 30
> > different QSPI flashes from four distinct vendors (Miron, Winbond,
> Macronix, and ISSI).
> >
> 
> Great.
> 
> >> What I'm interested is if each flash is in its own package. Are they?
> >
> > I'm sorry, but I don't quite understand what you mean by "if each
> > flash in its own package."
> >
> 
> There are flashes that are stacked at the physical level. It's a single flash with
> multiple dies, that are all under a single physical package.

Got it. The W25H02JV QSPI flash I mentioned earlier is a device with 
with four dies that are stacked at the physical level.

> 
> As I understand, your stacked flash model is at logical level. You have
> 2 flashes each in its own package. 2 different entities. Is my understanding
> correct?

Yes, that’s correct.

I'd like to contribute to your earlier point regarding the placement of 
the stacked layer. As you correctly highlighted, it should be in the 
spi-mem generic layer. For instance, when a read/write operation extends 
across multiple flashes (whether SPI-NOR or SPI-NAND), the stacked layer 
must handle the flash crossover. This requires setting the appropriate CS 
index in mem->spi->cs_index_mask to select the correct slave device and 
updating the data buffer, address & data length in spi_mem_op struct 
variable. Does this align with your understanding?

Regards,
Amit
> 
> Cheers,
> ta