[PATCH v3 2/8] dt-bindings: mtd: intel: lgm-nand: Fix maximum chip select value

[Miquel Raynal]

On Sat, 2022-07-02 at 23:12:21 UTC, Martin Blumenstingl wrote:
> The Intel LGM NAND IP only supports two chip selects: There's only two
> CS and ADDR_SEL register sets. Fix the maximum allowed chip select value
> according to the dt-bindings.
> 
> Fixes: 2f9cea8eae44f5 ("dt-bindings: mtd: Add Nand Flash Controller support for Intel LGM SoC")
> Acked-by: Rob Herring <robh at kernel.org>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl at googlemail.com>

Applied to https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git nand/next, thanks.

Miquel