[PATCH v2] mtd: spi-nor: core: Ignore -ENOTSUPP in spi_nor_init()

[Mika Westerberg]

Hi,

On Mon, Oct 03, 2022 at 05:52:42AM +0000, Tudor.Ambarus at microchip.com wrote:
> On 10/3/22 08:21, Mika Westerberg wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> > 
> > Hi,
> > 
> > On Mon, Oct 03, 2022 at 05:04:26AM +0000, Tudor.Ambarus at microchip.com wrote:
> >> On 9/23/22 12:34, Mika Westerberg wrote:
> >>
> >> Hi, Mika,
> >>
> >>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >>>
> >>> The Intel SPI-NOR controller does not support the 4-byte address opcode
> >>> so ->set_4byte_addr_mode() ends up returning -ENOTSUPP and the SPI flash
> >>> chip probe fail like this:
> >>>
> >>>   [ 12.291082] spi-nor: probe of spi0.0 failed with error -524
> >>>
> >>> Whereas previously before commit 08412e72afba ("mtd: spi-nor: core:
> >>> Return error code from set_4byte_addr_mode()") it worked just fine.
> >>>
> >>> Fix this by ignoring -ENOTSUPP in spi_nor_init().
> >>>
> >>> Fixes: 08412e72afba ("mtd: spi-nor: core: Return error code from set_4byte_addr_mode()")
> >>> Cc: stable at vger.kernel.org
> >>> Reported-by: Hongyu Ning <hongyu.ning at intel.com>
> >>> Signed-off-by: Mika Westerberg <mika.westerberg at linux.intel.com>
> >>> ---
> >>> The previous version of the patch (the revert) can be found here:
> >>>
> >>>   https://lore.kernel.org/linux-mtd/20220922134824.46758-1-mika.westerberg@linux.intel.com/
> >>>
> >>> In this version we ignore -ENOTSUPP but the other error codes will be
> >>> passed to the caller.
> >>>
> >>>  drivers/mtd/spi-nor/core.c | 4 +++-
> >>>  1 file changed, 3 insertions(+), 1 deletion(-)
> >>>
> >>> diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
> >>> index f2c64006f8d7..bee8fc4c9f07 100644
> >>> --- a/drivers/mtd/spi-nor/core.c
> >>> +++ b/drivers/mtd/spi-nor/core.c
> >>> @@ -2724,7 +2724,9 @@ static int spi_nor_init(struct spi_nor *nor)
> >>>                  */
> >>>                 WARN_ONCE(nor->flags & SNOR_F_BROKEN_RESET,
> >>>                           "enabling reset hack; may not recover from unexpected reboots\n");
> >>> -               return nor->params->set_4byte_addr_mode(nor, true);
> >>> +               err = nor->params->set_4byte_addr_mode(nor, true);
> >>> +               if (err && err != -ENOTSUPP)
> >>> +                       return err;
> >>>         }
> >>
> >> So as of now if you use a flash larger than 16 MBytes, you can't
> >> access above 16 MBytes, right? What happens at the controller side
> >> when it receives a nor->addr_nbytes of value 4?
> > 
> > The Intel controller does not really expose any of these operations to
> > the CPU so the only thing the driver can do is to tell the SPI-NOR core
> > that this is not supported.
> 
> That would be good. And you'll get a non-working flash anyway. But I was
> asking something else. There should be an address register in the controller.
> If you write 4 address bytes, the forth is ignored, or why does it work? You'll
> at least get inconsistent results and always write in the first 16 Mbytes regardless
> of the value of the 4th byte of address.

It works because the Intel SPI controller is not a real "SPI" controller
so instead of all the low lever operations it simply exposes bunch of
high-level commands such as read and write. All the rest is handled
internally by the controller so it knows (I think based on the SFDP
information and possibly something else part of the BIOS image) the
supported address length.

> >>
> >> Shouldn't spi_mem_supports_op() trim the 4-byte ops?
> >>
> >> The better fix to me would be to extend the SPI NOR core to support the Extended Address
> >> Register which consists of the 4th byte of memory address when the flash is operated
> >> in 3-byte address mode.
> > 
> > This is also something the Intel controller does not expose to the CPU
> > so I'm not sure if I have any means to test this approach.
> 
> would you please remind me what you mean with "expose to the CPU"? I thought about
> that the intel-spi controller can inform the SPI NOR core that it doesn't support
> 4-byte addresses and then the core to take that information and use the EAR register.
> Would that be possible?

The controller only exposes a couple of high-level operations that we
can perform in software through the register interface. There is no way
to access EAR register or anything like that. This high-level commands
to read and write status register but that's pretty much all.

For completeness here are all the possible commands it supports (in
hardware sequencig mode which is the one used with the modern chips):

0 Read (1 up to 64 bytes by setting FDBC)
1 Reserved
2 Write (1 up to 64 bytes by setting FDBC)
3 4k Block Erase
4 64k Sector erase
5 Read SFDP
6 Read JEDEC ID
7 write status
8 read status
9 RPMC Op1
A RPMC Op2

> > 
> > My point is that currently all the Intel SPI users are basically broken
> > in v6.0 because of the commit 08412e72afba so shouldn't that be dealt
> > first and then look at any possible improments?
> 
> Right, I got you from the first time, I just wanted to highlight that the intel-spi
> controller and the SPI NOR core behave badly, and they should be fixed.
> Your patch fixes a regression of a somewhat working flash, so probably it should be
> applied for the time being. But I'd really love a proper fix.

I'm fine to have a "proper" fix but just wanted to mention that this is
real regression that is currently visible to users.