[PATCH v3 1/1] mtd: spi-nor: micron-st: Enable locking for mt25qu256a

[Tudor Ambarus]

On Thu, 20 Oct 2022 09:20:58 +0000, Eliav Farber wrote:
> mt25qu256a [1] uses the 4 bit Block Protection scheme and supports
> Top/Bottom protection via the BP and TB bits of the Status Register.
> BP3 is located in bit 6 of the Status Register.
> Tested on MT25QU256ABA8ESF-0SIT.
> 
> [1] https://www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/mt25q/die-rev-a/mt25q_qljs_u_256_aba_0.pdf
> 
> [...]

Applied to spi-nor/next, thanks!

[1/1] mtd: spi-nor: micron-st: Enable locking for mt25qu256a
      https://git.kernel.org/mtd/c/bcc0c61e6134

Best regards,
-- 
Tudor Ambarus <tudor.ambarus at microchip.com>