[PATCH v2 1/4] mtd: spinand: Add support continuous read mode
Miquel Raynal
miquel.raynal at bootlin.com
Thu May 19 09:08:50 PDT 2022
Hi Zhengxun,
zhengxunli.mxic at gmail.com wrote on Wed, 9 Feb 2022 17:10:19 +0800:
> The patch supports setting the "CONT" bit of the configuration
add support for
> register and adding a continuous read mode flag for identification.
It's not really a configuration register, it's capability flag.
>
> Signed-off-by: Zhengxun <zhengxunli.mxic at gmail.com>
> ---
> drivers/mtd/nand/spi/core.c | 11 +++++++++++
> include/linux/mtd/spinand.h | 2 ++
> 2 files changed, 13 insertions(+)
>
> diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c
> index 2c8685f1f2fa..dc2e1dc1dbee 100644
> --- a/drivers/mtd/nand/spi/core.c
> +++ b/drivers/mtd/nand/spi/core.c
> @@ -193,6 +193,17 @@ static int spinand_init_quad_enable(struct spinand_device *spinand)
> enable ? CFG_QUAD_ENABLE : 0);
> }
>
> +static int spinand_continuous_read_enable(struct spinand_device *spinand)
> +{
> + return spinand_upd_cfg(spinand, CFG_CONT_READ_ENABLE,
> + CFG_CONT_READ_ENABLE);
> +}
> +
> +static int spinand_continuous_read_disable(struct spinand_device *spinand)
> +{
> + return spinand_upd_cfg(spinand, CFG_CONT_READ_ENABLE, 0);
> +}
> +
> static int spinand_ecc_enable(struct spinand_device *spinand,
> bool enable)
> {
> diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h
> index 6988956b8492..04be10ec8fb0 100644
> --- a/include/linux/mtd/spinand.h
> +++ b/include/linux/mtd/spinand.h
> @@ -154,6 +154,7 @@
> #define REG_CFG 0xb0
> #define CFG_OTP_ENABLE BIT(6)
> #define CFG_ECC_ENABLE BIT(4)
> +#define CFG_CONT_READ_ENABLE BIT(2)
> #define CFG_QUAD_ENABLE BIT(0)
>
> /* status register */
> @@ -307,6 +308,7 @@ struct spinand_ecc_info {
>
> #define SPINAND_HAS_QE_BIT BIT(0)
> #define SPINAND_HAS_CR_FEAT_BIT BIT(1)
> +#define SPINAND_HAS_CONT_READ_BIT BIT(2)
Not related to this patch.
>
> /**
> * struct spinand_ondie_ecc_conf - private SPI-NAND on-die ECC engine structure
Thanks,
Miquèl
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