[PATCH v8 3/5] mtd: Add support for HyperBus memory devices

[Geert Uytterhoeven]

Hi Vignesh,

On Sat, Jul 2, 2022 at 7:10 PM Raghavendra, Vignesh <vigneshr at ti.com> wrote:
> On 6/27/2022 8:58 PM, Geert Uytterhoeven wrote:
> > On Tue, Jun 25, 2019 at 10:00 AM Vignesh Raghavendra <vigneshr at ti.com> wrote:
> >> Cypress' HyperBus is Low Signal Count, High Performance Double Data Rate
> >> Bus interface between a host system master and one or more slave
> >> interfaces. HyperBus is used to connect microprocessor, microcontroller,
> >> or ASIC devices with random access NOR flash memory (called HyperFlash)
> >> or self refresh DRAM (called HyperRAM).
> >>
> >> Its a 8-bit data bus (DQ[7:0]) with  Read-Write Data Strobe (RWDS)
> >> signal and either Single-ended clock(3.0V parts) or Differential clock
> >> (1.8V parts). It uses ChipSelect lines to select b/w multiple slaves.
> >> At bus level, it follows a separate protocol described in HyperBus
> >> specification[1].
> >>
> >> HyperFlash follows CFI AMD/Fujitsu Extended Command Set (0x0002) similar
> >> to that of existing parallel NORs. Since HyperBus is x8 DDR bus,
> >> its equivalent to x16 parallel NOR flash with respect to bits per clock
> >> cycle. But HyperBus operates at >166MHz frequencies.
> >> HyperRAM provides direct random read/write access to flash memory
> >> array.
> >>
> >> But, HyperBus memory controllers seem to abstract implementation details
> >> and expose a simple MMIO interface to access connected flash.
> >>
> >> Add support for registering HyperFlash devices with MTD framework. MTD
> >> maps framework along with CFI chip support framework are used to support
> >> communicating with flash.
> >>
> >> Framework is modelled along the lines of spi-nor framework. HyperBus
> >> memory controller (HBMC) drivers calls hyperbus_register_device() to
> >> register a single HyperFlash device. HyperFlash core parses MMIO access
> >> information from DT, sets up the map_info struct, probes CFI flash and
> >> registers it with MTD framework.
> >>
> >> Some HBMC masters need calibration/training sequence[3] to be carried
> >> out, in order for DLL inside the controller to lock, by reading a known
> >> string/pattern. This is done by repeatedly reading CFI Query
> >> Identification String. Calibration needs to be done before trying to detect
> >> flash as part of CFI flash probe.
> >>
> >> HyperRAM is not supported at the moment.
> >
> > Thanks for your patch, which is now commit dcc7d3446a0fa19b ("mtd:
> > Add support for HyperBus memory devices") in v5.3.
> >
> >> HyperBus specification can be found at[1]
> >> HyperFlash datasheet can be found at[2]
> >>
> >> [1] https://www.cypress.com/file/213356/download
> >> [2] https://www.cypress.com/file/213346/download
> >> [3] http://www.ti.com/lit/ug/spruid7b/spruid7b.pdf
> >>     Table 12-5741. HyperFlash Access Sequence
> >
> > The last link no longer works.  Do you have a replacement?
>
> Looks like I used a link point to specific version instead of top level
> redirector link. Please use:
>
> https://www.ti.com/lit/pdf/spruid7

Thank you, that link works for me.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds