[PATCH v7 3/3] mtd: spi-nor: spansion: Add s25hl-t/s25hs-t IDs and fixups
Tudor.Ambarus at microchip.com
Tudor.Ambarus at microchip.com
Fri Jan 28 02:27:32 PST 2022
On 7/19/21 11:03, tkuw584924 at gmail.com wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> From: Takahiro Kuwano <Takahiro.Kuwano at infineon.com>
>
> The S25HL-T/S25HS-T family is the Cypress Semper Flash with Quad SPI.
>
> For the single-die package parts (512Mb and 1Gb), only bottom 4KB and
> uniform sector sizes are supported. This is due to missing or incorrect
> entries in SMPT. Fixup for other sector sizes configurations will be
> followed up as needed.
>
> Tested on Xilinx Zynq-7000 FPGA board.
>
> Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano at infineon.com>
> ---
> Changes in v7:
> - Add missing device info table in v6
>
> Changes in v6:
> - Remove 2Gb multi die pacakge support
>
> Changes in v5:
> - Add NO_CHIP_ERASE flag to S25HL02GT and S25HS02GT
>
> Changes in v4:
> - Merge block comments about SMPT in s25hx_t_post_sfdp_fixups()
> - Remove USE_CLSR flags from S25HL02GT and S25HS02GT
>
> Changes in v3:
> - Remove S25HL256T and S25HS256T
> - Add S25HL02GT and S25HS02GT
> - Add support for multi-die package parts support
> - Remove erase_map fix for top/split sector layout
> - Set ECC data unit size (16B) to writesize
>
> drivers/mtd/spi-nor/spansion.c | 90 ++++++++++++++++++++++++++++++++++
> 1 file changed, 90 insertions(+)
>
> diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c
> index ca50e77b4220..c7170477e706 100644
> --- a/drivers/mtd/spi-nor/spansion.c
> +++ b/drivers/mtd/spi-nor/spansion.c
> @@ -220,6 +220,84 @@ static int spansion_quad_enable_volatile(struct spi_nor *nor, u8 reg_dummy)
> return 0;
> }
>
> +static int s25hx_t_quad_enable(struct spi_nor *nor)
> +{
> + int ret = spansion_quad_enable_volatile(nor, 0);
> +
> + /* Reset WEL bit in any error cases */
the comment suggests an if (ret) then spi_nor_write_disable(nor);
Should you call write disable in all cases or just in case of errors?
> + spi_nor_write_disable(nor);
> +
> + return ret;
> +}
> +
> +static int
> +s25hx_t_post_bfpt_fixups(struct spi_nor *nor,
> + const struct sfdp_parameter_header *bfpt_header,
> + const struct sfdp_bfpt *bfpt)
> +{
> + int ret;
> + u32 addr;
> + u8 cfr3v;
> +
> + ret = spi_nor_set_4byte_addr_mode(nor, true);
why don't you let the core handle this for you? Why do you call it here?
> + if (ret)
> + return ret;
> + nor->addr_width = 4;
so SFDP gets the addr_width wrong?
> +
> + /* Replace Quad Enable with volatile version */
> + nor->params->quad_enable = s25hx_t_quad_enable;
> +
> + /*
> + * The page_size is set to 512B from BFPT, but it actually depends on
> + * the configuration register. Look up the CFR3V and determine the
> + * page_size.
> + */
> + ret = spansion_read_any_reg(nor, addr + SPINOR_REG_CYPRESS_CFR3V,
> + nor->addr_width, 0, &cfr3v);
> + if (ret)
> + return ret;
> +
> + if (!(cfr3v & SPINOR_REG_CYPRESS_CFR3V_PGSZ))
> + nor->params->page_size = 256;
> + else
> + nor->params->page_size = 512;
isn't the else case already covered by BFPT?
> +
> + return 0;
> +}
> +
> +void s25hx_t_post_sfdp_fixups(struct spi_nor *nor)
> +{
> + /* Fast Read 4B requires mode cycles */
> + nor->params->reads[SNOR_CMD_READ_FAST].num_mode_clocks = 8;
Is the BFPT wrong? Why do you update the num_mode_clocks here?
> +
> + /* The writesize should be ECC data unit size */
> + nor->params->writesize = 16;
> +
> + /*
> + * For the single-die package parts (512Mb and 1Gb), bottom 4KB and
> + * uniform sector maps are correctly populated in the erase_map
> + * structure. The table below shows all possible combinations of related
> + * register bits and its availability in SMPT.
> + *
> + * CFR3[3] | CFR1[6] | CFR1[2] | Sector Map | Available in SMPT?
> + * -------------------------------------------------------------------
> + * 0 | 0 | 0 | Bottom | YES
> + * 0 | 0 | 1 | Top | NO (decoded as Split)
> + * 0 | 1 | 0 | Split | NO
> + * 0 | 1 | 1 | Split | NO (decoded as Top)
> + * 1 | 0 | 0 | Uniform | YES
> + * 1 | 0 | 1 | Uniform | NO
> + * 1 | 1 | 0 | Uniform | NO
> + * 1 | 1 | 1 | Uniform | NO
> + * -------------------------------------------------------------------
> + */
did you miss to update erases here?
> +}
> +
> +static struct spi_nor_fixups s25hx_t_fixups = {
> + .post_bfpt = s25hx_t_post_bfpt_fixups,
> + .post_sfdp = s25hx_t_post_sfdp_fixups
> +};
> +
> /**
> * spi_nor_cypress_octal_dtr_enable() - Enable octal DTR on Cypress flashes.
> * @nor: pointer to a 'struct spi_nor'
> @@ -468,6 +546,18 @@ static const struct flash_info spansion_parts[] = {
> { "s25fl256l", INFO(0x016019, 0, 64 * 1024, 512,
> SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
> SPI_NOR_4B_OPCODES) },
> + { "s25hl512t", INFO6(0x342a1a, 0x0f0390, 256 * 1024, 256,
> + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR)
> + .fixups = &s25hx_t_fixups },
> + { "s25hl01gt", INFO6(0x342a1b, 0x0f0390, 256 * 1024, 512,
> + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR)
> + .fixups = &s25hx_t_fixups },
> + { "s25hs512t", INFO6(0x342b1a, 0x0f0390, 256 * 1024, 256,
> + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR)
> + .fixups = &s25hx_t_fixups },
> + { "s25hs01gt", INFO6(0x342b1b, 0x0f0390, 256 * 1024, 512,
> + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR)
> + .fixups = &s25hx_t_fixups },
> { "cy15x104q", INFO6(0x042cc2, 0x7f7f7f, 512 * 1024, 1,
> SPI_NOR_NO_ERASE) },
> { "s28hs512t", INFO(0x345b1a, 0, 256 * 1024, 256,
> --
> 2.25.1
>
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