[PATCH v10 03/13] spi: cadence-quadspi: Provide a capability structure
Miquel Raynal
miquel.raynal at bootlin.com
Thu Jan 27 01:17:58 PST 2022
This controller has DTR support, so advertize it with a capability now
that the spi-controller structure contains this new field. This will
later be used by the core to discriminate whether an operation is
supported or not, in a more generic way than having different helpers.
Signed-off-by: Miquel Raynal <miquel.raynal at bootlin.com>
Reviewed-by: Pratyush Yadav <p.yadav at ti.com>
Reviewed-by: Boris Brezillon <boris.brezillon at collabora.com>
Link: https://lore.kernel.org/linux-mtd/20220104083631.40776-4-miquel.raynal@bootlin.com
---
drivers/spi/spi-cadence-quadspi.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
index b808c94641fa..455b90d1feed 100644
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -1595,6 +1595,10 @@ static const struct spi_controller_mem_ops cqspi_mem_ops = {
.supports_op = cqspi_supports_mem_op,
};
+static const struct spi_controller_mem_caps cqspi_mem_caps = {
+ .dtr = true,
+};
+
static int cqspi_setup_flash(struct cqspi_st *cqspi)
{
struct platform_device *pdev = cqspi->pdev;
@@ -1652,6 +1656,7 @@ static int cqspi_probe(struct platform_device *pdev)
}
master->mode_bits = SPI_RX_QUAD | SPI_RX_DUAL;
master->mem_ops = &cqspi_mem_ops;
+ master->mem_caps = &cqspi_mem_caps;
master->dev.of_node = pdev->dev.of_node;
cqspi = spi_master_get_devdata(master);
--
2.27.0
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