[PATCH] mtd: spi-nor: spansion: Add support for Infineon S25FS256T

[Takahiro Kuwano]

On 12/19/2022 5:27 PM, Michael Walle wrote:
> Hi,
> 
> Am 2022-12-19 08:29, schrieb Michael Walle:
>> Am 2022-12-19 02:55, schrieb tkuw584924 at gmail.com:
>>> From: Takahiro Kuwano <Takahiro.Kuwano at infineon.com>
>>>
>>> Infineon S25FS256T is 256Mbit Quad SPI NOR flash. The key features and
>>> differences comparing to other Spansion/Cypress flash familes are:
>>>   - 4-byte address mode by factory default
>>>   - Quad mode is enabled by factory default
>>>   - Supports mixture of 128KB and 64KB sectors by OTP configuration
>>>     (this patch supports uniform 128KB only due to complexity of
>>>      non-uniform layout)
>>>
>>> Tested on Xilinx Zynq-7000 FPGA board.
>>>
>>> Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano at infineon.com>
>>> ---
>>> Datasheet:
>>> fileId=8ac78c8c80027ecd0180740c5a46707https://www.infineon.com/dgdlac/Infineon-S25FS256T_256Mb_SEMPER_Nano_Flash_Quad_SPI_1.8V-DataSheet-v12_00-EN.pdf?a
> 
> This should be a Link: tag in the commit message.
> 
Thank you!

>> Also I'm not sure when set_4byte_addr_mode() is called during init.
>> It seems slightly wrong to me because it will check wether
>> SNOR_F_4B_OPCODES is set. But in the restore path, it is checked for
>> !SNOR_F_4B_OPCODES before 3 byte mode is enabled again. Mhh.
> 
> Scrap that comment. I read the code wrong. The place I looked at
> just translate the 3B opcodes to the 4B ones.
> 
> -michael