[PATCH 8/8] mtd: spi-nor: spansion: Add support for Infineon

[Tudor.Ambarus at microchip.com]

On 8/8/22 08:42, Takahiro Kuwano wrote:
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> 
> On 8/8/2022 1:47 PM, Tudor.Ambarus at microchip.com wrote:
>> On 8/6/22 09:34, tkuw584924 at gmail.com wrote:
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>>> From: Takahiro Kuwano <Takahiro.Kuwano at infineon.com>
>>
>> Hi!
>>
>>>
>>> s25hl02gt and s25hs02gt
>>>
>>> Add ID, flags, and fixup for s25hl02gt and s25hs02gt.
>>> These parts are
>>>   - Dual-die package parts
>>>   - Not support chip erase
>>>   - 4-byte addressing mode by default
>>
>> CFR2N[7] CFR2V[7] says that: "For the DDP or QDP devices, if ADRBYT = 0
>> only the first 128 Mb of die 1 can be accessed."
>> So there are flashes of the same family that are by default in 3 byte address
>> mode. You added support just for a subset of them and used a generic name,
>> which is not accurate, right?
>>
> We added model #15 (3-byte address mode by default) to address special
> requirement from a customer who needs to use bootrom with 3-byte addressing.
> Anyway, I overlooked model # difference. Thanks for pointing out this.
> 
>> Can we instead make an algorithm to determine the current address mode?
>>
> I have just found that we can distinguish model # via BFPT DWORD16.
> If Hardware reset, Software reset, or Power cycle can exit 4-byte address
> mode, that means the device is 3-byte address mode by default.

I don't think this will help us. It doesn't matter the default mode if you
have a non volatile register that can be updated and changes the default
mode.

Are there any registers/data that can be read successively in 3 byte addr mode
and then in 4 byte addr mode? We'll then compare what we receive from the flash
with a known value and determine the mode.

> The questions is can we implement in spi_nor_parse_bfpt() in sfdp.c or
> post_bfpt_fixup() in manufacturer code?
> 


-- 
Cheers,
ta