[PATCH 8/8] mtd: spi-nor: spansion: Add support for Infineon

[Tudor.Ambarus at microchip.com]

On 8/6/22 09:34, tkuw584924 at gmail.com wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> From: Takahiro Kuwano <Takahiro.Kuwano at infineon.com>

Hi!

> 
> s25hl02gt and s25hs02gt
> 
> Add ID, flags, and fixup for s25hl02gt and s25hs02gt.
> These parts are
>   - Dual-die package parts
>   - Not support chip erase
>   - 4-byte addressing mode by default

CFR2N[7] CFR2V[7] says that: "For the DDP or QDP devices, if ADRBYT = 0
only the first 128 Mb of die 1 can be accessed."
So there are flashes of the same family that are by default in 3 byte address
mode. You added support just for a subset of them and used a generic name,
which is not accurate, right?

Can we instead make an algorithm to determine the current address mode?

-- 
Cheers,
ta