[PATCH] mtd: spi-nor: mt25qu: Ignore 6th ID byte

[Pratyush Yadav]

On 23/11/21 01:13PM, Alexander Sverdlin wrote:
> Dear maintainers!
> 
> On 22/11/2021 16:05, Michael Walle wrote:
> > Thanks, so that's the SFDP data for the mt25qu256aba8e12-1sit part. and the
> > jedec id is 20bb19104473, correct?
> 
> While we are at this part, I've encountered another issue:
> 
> The chip supports 1-1-1, 1-1-4 and 1-4-4 write OPs in extended SPI mode,
> while only 1-1-0 erase. (as well as 4-4-4/4-4-0, but that's not the issue here,
> I think).
> 
> Now the erase code (chip/sector) uses spi_nor_spimem_setup_op(nor, &op, nor->write_proto)
> in both functions.
> 
> In my opinion, as I look into Micron or Macronix datasheets, write_proto has little to
> do with erase_proto. (there is currently no separate erase_proto)

I think this just worked for most flashes since both writes and erases 
generally use 1-bit mode. 4 or 8 bit modes are generally used for reads 
only.

> 
> Before I come up with a totally wrong patch, wanted to ask your opinion, how should
> it be solved, what do you think?
> 
> I do not see any erase-related tables for this in JESD216C.
> I also cannot come up with an example of a chip with erase != 1-1-0.

See Micron MT35XU512ABA or Cypress S28HS512T (in spansion.c). Both have 
erase in 8D-8D-8D mode.

> 
> Shall I hardcode 1-1-0 for erase?
> Shall I introduce erase_proto? What would be the logic for its setting/discovery?

I think introducing erase_proto would be the sensible thing. You would 
have to see if we can discover erase protocol from SFDP. But my question 
is: is that really worth it? Do you really need that little bit speed 
boost you'd get by transmitting write data in 4 bit mode, since the 
large portion of the time would be spent in the chip actually flashing 
the data.

-- 
Regards,
Pratyush Yadav
Texas Instruments Inc.