[RFC PATCH 0/3] Dual stacked/parallel memories bindings

[Pratyush Yadav]

On 12/11/21 04:24PM, Miquel Raynal wrote:
> Hello Rob, Mark, Tudor & Pratyush,
> 
> Here is an RFC to open the discussion about the sensitive task of
> supporting specific SPI controller modes like Xilinx's where the
> controller can highly abstract the hardware and provide access to a
> single bigger device instead. I'll let you go through the series and
> tell me what you think.
> 
> I think there are two possible approaches:
> 1- Describe the two devices as being a single one which is what we will
>    get from the controller anyway (implies supporting two CS per SPI
>    device)
> or
> 2- Describe the two devices in the device tree and then by software hack
>    into the MTD core to simulate a single device to talk to.

Approach 1 makes more sense to me since once we implement it you can 
also use such multi-CS flashes with "dumber" controllers as well like 
spi-cadence-quadspi. There, the driver would have to manually set the 
chip select instead of it being done automatically by looking at the top 
bit. This would at least work for the dual-stacked memories.

How I envision this being implemented is that SPI NOR would be aware of 
the number of Chip Selects and when to use which one, and it would 
specify the CS value in the SPI MEM op. The controller driver can then 
execute this op as needed. One point to note here is that the entire 
memory won't be read in a single transaction. There would be 2 
transactions: one with CS=0 and one with CS=1. Is this fine for you? Do 
you have something else in mind?

I am not sure how this model would work for a dual-parallel memory 
though.

> 
> I have looked at the code, there is no good solution, but #2 definitely
> looks horribly complicated and subject to a lot of corner cases to
> handle, hence this proposal to go for solution #1.
> 
> Cheers,
> Miquèl
> 
> Miquel Raynal (3):
>   spi: dt-bindings: Allow describing flashes with two CS
>   dt-binding: mtd: spi-nor: Allow two CS per device
>   spi: dt-bindings: zynqmp: Describe dual stacked/parallel memories
>     modes
> 
>  .../bindings/mtd/jedec,spi-nor.yaml           |  2 +-
>  .../bindings/spi/spi-controller.yaml          |  6 ++--
>  .../bindings/spi/spi-zynqmp-qspi.yaml         | 31 +++++++++++++++++++
>  scripts/dtc/checks.c                          | 24 ++++++++------
>  4 files changed, 50 insertions(+), 13 deletions(-)
> 
> -- 
> 2.27.0
> 

-- 
Regards,
Pratyush Yadav
Texas Instruments Inc.