[RFC PATCH 3/3] spi: dt-bindings: zynqmp: Describe dual stacked/parallel memories modes
Miquel Raynal
miquel.raynal at bootlin.com
Fri Nov 12 07:24:11 PST 2021
Describe the two dual memories modes which are available on the ZynqMP
QSPI controller: stacked and parallel.
Signed-off-by: Miquel Raynal <miquel.raynal at bootlin.com>
---
.../bindings/spi/spi-zynqmp-qspi.yaml | 31 +++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml b/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml
index ea72c8001256..959e008602f5 100644
--- a/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml
+++ b/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml
@@ -30,6 +30,28 @@ properties:
clocks:
maxItems: 2
+ xlnx,dual-stacked-memories:
+ type: boolean
+ description: The QSPI controller can be wired to two SPI memorie in stacked
+ mode. This basically means that the two devices share the same bus but
+ have their own chip-select. From the controller perspective, it is like
+ having a single big device, the most significant addressing bit
+ automatically driving one chip-select or the other. This basically doubles
+ the total address space with only a single additional wire. Note that when
+ configured in dual-stacked mode, the controller does not support XIP nor
+ linear addressing.
+
+ xlnx,dual-parallel-memories:
+ type: boolean
+ description: The QSPI controller can be wired to two SPI memorie in parallel
+ mode. The two devices physically are on different buses but will always
+ act synchronously as for each byte, the even bits are stored in one memory
+ and the odd bits are stored in the other. From the controller perspective,
+ it is like having a single big device with a much higher throughput. This
+ basically uses two quad devices as if it was a single octal device. Note
+ that when configured in dual-parallel mode, the controller does not
+ support XIP nor linear addressing.
+
unevaluatedProperties: false
examples:
@@ -47,5 +69,14 @@ examples:
interrupt-parent = <&gic>;
reg = <0x0 0xff0f0000 0x0 0x1000>,
<0x0 0xc0000000 0x0 0x8000000>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ xlnx,dual-stacked-memories;
+
+ flash at 0,1 {
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
+ reg = <0>, <1>;
+ };
};
};
--
2.27.0
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