[RFC PATCH 0/3] Dual stacked/parallel memories bindings

[Miquel Raynal]

Hello Rob, Mark, Tudor & Pratyush,

Here is an RFC to open the discussion about the sensitive task of
supporting specific SPI controller modes like Xilinx's where the
controller can highly abstract the hardware and provide access to a
single bigger device instead. I'll let you go through the series and
tell me what you think.

I think there are two possible approaches:
1- Describe the two devices as being a single one which is what we will
   get from the controller anyway (implies supporting two CS per SPI
   device)
or
2- Describe the two devices in the device tree and then by software hack
   into the MTD core to simulate a single device to talk to.

I have looked at the code, there is no good solution, but #2 definitely
looks horribly complicated and subject to a lot of corner cases to
handle, hence this proposal to go for solution #1.

Cheers,
Miquèl

Miquel Raynal (3):
  spi: dt-bindings: Allow describing flashes with two CS
  dt-binding: mtd: spi-nor: Allow two CS per device
  spi: dt-bindings: zynqmp: Describe dual stacked/parallel memories
    modes

 .../bindings/mtd/jedec,spi-nor.yaml           |  2 +-
 .../bindings/spi/spi-controller.yaml          |  6 ++--
 .../bindings/spi/spi-zynqmp-qspi.yaml         | 31 +++++++++++++++++++
 scripts/dtc/checks.c                          | 24 ++++++++------
 4 files changed, 50 insertions(+), 13 deletions(-)

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2.27.0