[RFC PATCH 1/3] spi: dt-bindings: Allow describing flashes with two CS

[Miquel Raynal]

The Xilinx QSPI controller has two advanced modes which allow the
controller to behave differently and consider two flashes as one single
storage.

One of these two modes is quite complex to support from a binding point
of view and is the dual parallel memories. In this mode, each byte of
data is stored in both devices: the even bits in one, the odd bits in
the other. The split is automatically handled by the QSPI controller and
is transparent for the user.

The other mode is simpler to support, it is called dual stacked
memories. The controller shares the same SPI bus but each of the devices
contain half of the data. Once in this mode, the controller does not
follow CS requests but instead internally wires the two CSlevels with
the value of the most significant address bit.

Supporting these two modes will involve core changes which include the
possibility of providing two CS for a single SPI device.

Signed-off-by: Miquel Raynal <miquel.raynal at bootlin.com>
---
 .../bindings/spi/spi-controller.yaml          |  6 ++---
 scripts/dtc/checks.c                          | 24 ++++++++++++-------
 2 files changed, 18 insertions(+), 12 deletions(-)

diff --git a/Documentation/devicetree/bindings/spi/spi-controller.yaml b/Documentation/devicetree/bindings/spi/spi-controller.yaml
index 8246891602e7..51877b637bfe 100644
--- a/Documentation/devicetree/bindings/spi/spi-controller.yaml
+++ b/Documentation/devicetree/bindings/spi/spi-controller.yaml
@@ -20,7 +20,7 @@ properties:
     pattern: "^spi(@.*|-[0-9a-f])*$"
 
   "#address-cells":
-    enum: [0, 1]
+    enum: [0, 1, 2]
 
   "#size-cells":
     const: 0
@@ -91,7 +91,7 @@ properties:
       - compatible
 
 patternProperties:
-  "^.*@[0-9a-f]+$":
+  "^.*@[0-9a-f]+,?[0-9a-f]*$":
     type: object
 
     properties:
@@ -174,7 +174,7 @@ allOf:
     then:
       properties:
         "#address-cells":
-          const: 1
+          enum: [1, 2]
     else:
       properties:
         "#address-cells":
diff --git a/scripts/dtc/checks.c b/scripts/dtc/checks.c
index 781ba1129a8e..4eaa925c3442 100644
--- a/scripts/dtc/checks.c
+++ b/scripts/dtc/checks.c
@@ -1094,7 +1094,7 @@ static const struct bus_type spi_bus = {
 
 static void check_spi_bus_bridge(struct check *c, struct dt_info *dti, struct node *node)
 {
-	int spi_addr_cells = 1;
+	int spi_addr_cells = 2;
 
 	if (strprefixeq(node->name, node->basenamelen, "spi")) {
 		node->bus = &spi_bus;
@@ -1125,7 +1125,7 @@ static void check_spi_bus_bridge(struct check *c, struct dt_info *dti, struct no
 
 	if (get_property(node, "spi-slave"))
 		spi_addr_cells = 0;
-	if (node_addr_cells(node) != spi_addr_cells)
+	if (node_addr_cells(node) > spi_addr_cells)
 		FAIL(c, dti, node, "incorrect #address-cells for SPI bus");
 	if (node_size_cells(node) != 0)
 		FAIL(c, dti, node, "incorrect #size-cells for SPI bus");
@@ -1137,8 +1137,8 @@ static void check_spi_bus_reg(struct check *c, struct dt_info *dti, struct node
 {
 	struct property *prop;
 	const char *unitname = get_unitname(node);
-	char unit_addr[9];
-	uint32_t reg = 0;
+	char unit_addr[18];
+	uint32_t reg0 = 0, reg1 = 0;
 	cell_t *cells = NULL;
 
 	if (!node->parent || (node->parent->bus != &spi_bus))
@@ -1156,11 +1156,17 @@ static void check_spi_bus_reg(struct check *c, struct dt_info *dti, struct node
 		return;
 	}
 
-	reg = fdt32_to_cpu(*cells);
-	snprintf(unit_addr, sizeof(unit_addr), "%x", reg);
-	if (!streq(unitname, unit_addr))
-		FAIL(c, dti, node, "SPI bus unit address format error, expected \"%s\"",
-		     unit_addr);
+	reg0 = fdt32_to_cpu(cells[0]);
+	snprintf(unit_addr, sizeof(unit_addr), "%x", reg0);
+	if (!streq(unitname, unit_addr)) {
+		reg1 = fdt32_to_cpu(cells[1]);
+		snprintf(unit_addr, sizeof(unit_addr), "%x,%x", reg0, reg1);
+		if (!streq(unitname, unit_addr)) {
+			FAIL(c, dti, node,
+			     "SPI bus unit address format error, expected \"%s\"",
+			     unit_addr);
+		}
+	}
 }
 WARNING(spi_bus_reg, check_spi_bus_reg, NULL, &reg_format, &spi_bus_bridge);
 
-- 
2.27.0