[RFC PATCH 0/6] spi: Add OSPI PHY calibration support for spi-cadence-quadspi

[Tudor.Ambarus at microchip.com]

On 3/12/21 3:32 PM, Michael Walle wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> Am 2021-03-11 20:12, schrieb Pratyush Yadav:
>> The main problem here is telling the controller where to find the
>> pattern and how to read it. This RFC uses nvmem cells which point to a
>> fixed partition containing the data to do the reads. It depends on [0]
>> and [1].
>>
>> The obvious problem with this is it won't work when the partitions are
>> defined via command line. I don't see any good way to add nvmem cells
>> to
>> command line partitions. I would like some help or ideas here. We don't
>> necessarily have to use nvmem either. Any way that can cleanly and
>> consistently let the controller find out where the pattern is stored is
>> good.
> 
> The NXP LS1028A SoC has a similar calibration (although there its done
> in hardware it seems) and there the datasheet mentions there are flash
> devices which supports a preamble before a read function. The preamble
> is then some kind of learning pattern. Did you see a flash which
> actually
> supports that in the wild? I can't find any publicly available

MX66LM1G45G is an example.

> datasheets> of 8bit I/O SPI NOR flashes