[PATCH 1/2] mtd: spi-nor: micron-st: sync flags of mt25ql02g and mt25qu02g with other mt25q

[Michael Walle]

Am 2021-07-27 12:45, schrieb Matthias Schiffer:
> On Tue, 2021-07-27 at 09:09 +0200, Michael Walle wrote:
[..]
>> > --- a/drivers/mtd/spi-nor/micron-st.c
>> > +++ b/drivers/mtd/spi-nor/micron-st.c
>> > @@ -181,11 +181,11 @@ static const struct flash_info st_parts[] = {
>> >  			      SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |
>> >  			      NO_CHIP_ERASE) },
>> >  	{ "mt25ql02g",   INFO(0x20ba22, 0, 64 * 1024, 4096,
>> > -			      SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |
>> > -			      NO_CHIP_ERASE) },
>> 
>> This bothers me. I'm not sure how this will work. I see that
>> chip erase is command 0xc7, but both the new and the old flash
>> just supports 0xc3 (DIE ERASE). Did you test these changes?
> 
> Thanks for catching this. I overlooked that the 1G and 2G variants
> don't support the same erase commands as the smaller versions after
> all... It is possible that I only tested this with partitioned MTD, so
> I didn't hit the whole-chip erase case.
> 
> Which command should I use to test the chip erase? Will a `flash_erase
> /dev/mtdX 0 0` trigger the correct operation?

I guess so. Looking at
http://git.infradead.org/mtd-utils.git/blob/HEAD:/misc-utils/flash_erase.c#l226

It seems you should see a different output for either erasing individual
sectors or the whole chip (as long as the kernel doesn't the invidual
block erase itself).

-michael