[PATCH] mtd: nand: spi: Support GigaDevice GD5F1GQ5UExxG
Stefan Roese
sr at denx.de
Thu Feb 11 04:26:34 EST 2021
On 10.02.21 18:00, Reto Schneider wrote:
> From: Reto Schneider <reto.schneider at husqvarnagroup.com>
>
> The relevant changes to the already existing GD5F1GQ4UExxG support has
> been determined by consulting the GigaDevice product change notice
> AN-0392-10, version 1.0 from November 30, 2020.
>
> As the overlaps are huge, variable names have been generalized
> accordingly.
>
> Apart form the lowered ECC strength (4 instead of 8 bits per 512 bytes),
> the new device ID, and the extra quad IO dummy byte, no changes had to
> be taken into account.
>
> New hardware features are not supported, namely:
> - Power on reset
> - Unique ID
> - Double transfer rate (DTR)
> - Parameter page
> - Random data quad IO
>
> The inverted semantic of the "driver strength" register bits, defaulting
> to 100% instead of 50% for the Q5 devices, got ignored as the driver has
> never touched them anyway.
>
> The no longer supported "read from cache during block erase"
> functionality I do not know how to reflect.
>
> Implementation has been tested on MediaTek MT7688 based GARDENA smart
> Gateways using both, GigaDevice GD5F1GQ5UEYIG and GD5F1GQ4UBYIG.
>
> Signed-off-by: Reto Schneider <reto.schneider at husqvarnagroup.com>
Looks very good, thanks:
Reviewed-by: Stefan Roese <sr at denx.de>
Thanks,
Stefan
> ---
> drivers/mtd/nand/spi/gigadevice.c | 69 +++++++++++++++++++++++++++----
> 1 file changed, 60 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/mtd/nand/spi/gigadevice.c b/drivers/mtd/nand/spi/gigadevice.c
> index 33c67403c4aa..1dd1c5898093 100644
> --- a/drivers/mtd/nand/spi/gigadevice.c
> +++ b/drivers/mtd/nand/spi/gigadevice.c
> @@ -13,7 +13,10 @@
> #define GD5FXGQ4XA_STATUS_ECC_1_7_BITFLIPS (1 << 4)
> #define GD5FXGQ4XA_STATUS_ECC_8_BITFLIPS (3 << 4)
>
> -#define GD5FXGQ4UEXXG_REG_STATUS2 0xf0
> +#define GD5FXGQ5XE_STATUS_ECC_1_4_BITFLIPS (1 << 4)
> +#define GD5FXGQ5XE_STATUS_ECC_4_BITFLIPS (3 << 4)
> +
> +#define GD5FXGQXXEXXG_REG_STATUS2 0xf0
>
> #define GD5FXGQ4UXFXXG_STATUS_ECC_MASK (7 << 4)
> #define GD5FXGQ4UXFXXG_STATUS_ECC_NO_BITFLIPS (0 << 4)
> @@ -102,7 +105,7 @@ static int gd5fxgq4xa_ecc_get_status(struct spinand_device *spinand,
> return -EINVAL;
> }
>
> -static int gd5fxgq4_variant2_ooblayout_ecc(struct mtd_info *mtd, int section,
> +static int gd5fxgqx_variant2_ooblayout_ecc(struct mtd_info *mtd, int section,
> struct mtd_oob_region *region)
> {
> if (section)
> @@ -114,7 +117,7 @@ static int gd5fxgq4_variant2_ooblayout_ecc(struct mtd_info *mtd, int section,
> return 0;
> }
>
> -static int gd5fxgq4_variant2_ooblayout_free(struct mtd_info *mtd, int section,
> +static int gd5fxgqx_variant2_ooblayout_free(struct mtd_info *mtd, int section,
> struct mtd_oob_region *region)
> {
> if (section)
> @@ -127,9 +130,10 @@ static int gd5fxgq4_variant2_ooblayout_free(struct mtd_info *mtd, int section,
> return 0;
> }
>
> -static const struct mtd_ooblayout_ops gd5fxgq4_variant2_ooblayout = {
> - .ecc = gd5fxgq4_variant2_ooblayout_ecc,
> - .free = gd5fxgq4_variant2_ooblayout_free,
> +/* Valid for Q4/Q5 and Q6 (untested) devices */
> +static const struct mtd_ooblayout_ops gd5fxgqx_variant2_ooblayout = {
> + .ecc = gd5fxgqx_variant2_ooblayout_ecc,
> + .free = gd5fxgqx_variant2_ooblayout_free,
> };
>
> static int gd5fxgq4xc_ooblayout_256_ecc(struct mtd_info *mtd, int section,
> @@ -165,7 +169,7 @@ static int gd5fxgq4uexxg_ecc_get_status(struct spinand_device *spinand,
> u8 status)
> {
> u8 status2;
> - struct spi_mem_op op = SPINAND_GET_FEATURE_OP(GD5FXGQ4UEXXG_REG_STATUS2,
> + struct spi_mem_op op = SPINAND_GET_FEATURE_OP(GD5FXGQXXEXXG_REG_STATUS2,
> &status2);
> int ret;
>
> @@ -203,6 +207,43 @@ static int gd5fxgq4uexxg_ecc_get_status(struct spinand_device *spinand,
> return -EINVAL;
> }
>
> +static int gd5fxgq5xexxg_ecc_get_status(struct spinand_device *spinand,
> + u8 status)
> +{
> + u8 status2;
> + struct spi_mem_op op = SPINAND_GET_FEATURE_OP(GD5FXGQXXEXXG_REG_STATUS2,
> + &status2);
> + int ret;
> +
> + switch (status & STATUS_ECC_MASK) {
> + case STATUS_ECC_NO_BITFLIPS:
> + return 0;
> +
> + case GD5FXGQ5XE_STATUS_ECC_1_4_BITFLIPS:
> + /*
> + * Read status2 register to determine a more fine grained
> + * bit error status
> + */
> + ret = spi_mem_exec_op(spinand->spimem, &op);
> + if (ret)
> + return ret;
> +
> + /*
> + * 1 ... 4 bits are flipped (and corrected)
> + */
> + /* bits sorted this way (1...0): ECCSE1, ECCSE0 */
> + return ((status2 & STATUS_ECC_MASK) >> 4) + 1;
> +
> + case STATUS_ECC_UNCOR_ERROR:
> + return -EBADMSG;
> +
> + default:
> + break;
> + }
> +
> + return -EINVAL;
> +}
> +
> static int gd5fxgq4ufxxg_ecc_get_status(struct spinand_device *spinand,
> u8 status)
> {
> @@ -282,7 +323,7 @@ static const struct spinand_info gigadevice_spinand_table[] = {
> &write_cache_variants,
> &update_cache_variants),
> SPINAND_HAS_QE_BIT,
> - SPINAND_ECCINFO(&gd5fxgq4_variant2_ooblayout,
> + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
> gd5fxgq4uexxg_ecc_get_status)),
> SPINAND_INFO("GD5F1GQ4UFxxG",
> SPINAND_ID(SPINAND_READID_METHOD_OPCODE, 0xb1, 0x48),
> @@ -292,8 +333,18 @@ static const struct spinand_info gigadevice_spinand_table[] = {
> &write_cache_variants,
> &update_cache_variants),
> SPINAND_HAS_QE_BIT,
> - SPINAND_ECCINFO(&gd5fxgq4_variant2_ooblayout,
> + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
> gd5fxgq4ufxxg_ecc_get_status)),
> + SPINAND_INFO("GD5F1GQ5UExxG",
> + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x51),
> + NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
> + NAND_ECCREQ(4, 512),
> + SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
> + &write_cache_variants,
> + &update_cache_variants),
> + SPINAND_HAS_QE_BIT,
> + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
> + gd5fxgq5xexxg_ecc_get_status)),
> };
>
> static const struct spinand_manufacturer_ops gigadevice_spinand_manuf_ops = {
>
> base-commit: 92bf22614b21a2706f4993b278017e437f7785b3
>
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