[PATCH 2/2] mtd: spi-nor: disable 16-bit-sr for macronix

[Tudor.Ambarus at microchip.com]

On 12/27/21 11:16 AM, vincent at systemli.org wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> From: Nick Hainke <vincent at systemli.org>
> 
> Macronix flash chips seem to consist of only one status register.
> These chips will not work with the "16-bit Write Status (01h) Command".
> Disable SNOR_F_HAS_16BIT_SR for all Macronix chips.

Hi, Vincent!

Have you checked all the existing macronix flash_info entries and determined
that neither of them support SNOR_F_HAS_16BIT_SR? Per manufacturer settings
are a bit sensible because we can't predict what manufacturers are doing with
new flash designs and whether they'll respect their "legacy" flash settings or
not. Thus I'm a bit reluctant in adding per manufacturer settings.

Cheers,
ta

> 
> Tested with MX25L6405D.
> 
> Fixes: 39d1e3340c73 ("mtd: spi-nor: Fix clearing of QE bit on
> lock()/unlock()")
> 
> Signed-off-by: David Bauer <mail at david-bauer.net>
> Signed-off-by: Nick Hainke <vincent at systemli.org>
> ---
>  drivers/mtd/spi-nor/macronix.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c
> index f07b59a4120a..d530ab0b3b13 100644
> --- a/drivers/mtd/spi-nor/macronix.c
> +++ b/drivers/mtd/spi-nor/macronix.c
> @@ -94,6 +94,7 @@ static void macronix_default_init(struct spi_nor *nor)
>  {
>         nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable;
>         nor->params->set_4byte_addr_mode = spi_nor_set_4byte_addr_mode;
> +       nor->flags &= ~SNOR_F_HAS_16BIT_SR;
>  }
> 
>  static const struct spi_nor_fixups macronix_fixups = {
> --
> 2.34.1
> 
> 
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