[PATCH v2 5/5] spi: dt-bindings: Add an example with two stacked flashes

[Rob Herring]

On Mon, Nov 29, 2021 at 10:23:19AM +0100, Miquel Raynal wrote:
> Hi Rob,
> 
> robh at kernel.org wrote on Sun, 28 Nov 2021 10:55:06 -0600:
> 
> > On Sat, Nov 27, 2021 at 04:13:22PM -0700, Rob Herring wrote:
> > > On Fri, 26 Nov 2021 17:34:50 +0100, Miquel Raynal wrote:  
> > > > Provide an example of how to describe two flashes in eg. stacked mode.
> > > > 
> > > > Signed-off-by: Miquel Raynal <miquel.raynal at bootlin.com>
> > > > ---
> > > >  Documentation/devicetree/bindings/spi/spi-controller.yaml | 7 +++++++
> > > >  1 file changed, 7 insertions(+)
> > > >   
> > > 
> > > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
> > > on your patch (DT_CHECKER_FLAGS is new in v5.13):
> > > 
> > > yamllint warnings/errors:
> > > 
> > > dtschema/dtc warnings/errors:
> > > Documentation/devicetree/bindings/spi/spi-controller.example.dts:40.23-45.15: Warning (spi_bus_reg): /example-0/spi at 80010000/flash at 2,3: SPI bus unit address format error, expected "2"  
> > 
> > Unit-addresses are based on the first reg entry.
> 
> Yes, I believe this error is expected since dtc has not been yet
> updated. Below the patch for adapting dtc to this new situation and
> keep the robots happy.
> 
> How should we proceed?

No, I'm saying you have this wrong. A unit-address is composed of 
different fields, not different entries of the same field. For 
example, an external parallel bus has a chip select plus address, so the 
unit-address is '<cs>,<addr>'. If you have 2 SPI chip selects, that's 2 
entries of the same thing. The SPI bus is not 2 address cells, but 1 
cell with 2 entries.

Rob