[RESEND PATCH 1/2] mtd: spi-nor: do not touch TB bit without SPI_NOR_HAS_TB

[Vignesh Raghavendra]

On 9/30/20 6:37 PM, Ivan Mikhaylov wrote:
> On Wed, 2020-09-30 at 15:06 +0530, Vignesh Raghavendra wrote:
>>
>> On 9/21/20 4:54 PM, Ivan Mikhaylov wrote:
>>> Some chips like macronix don't have TB(Top/Bottom protection)
>>> bit in the status register. Do not write tb_mask inside status
>>> register, unless SPI_NOR_HAS_TB is present for the chip.
>>>
>>
>> Not entirely accurate.. Macronix chips have TB bit in config register
>> and is OTP and hence should not be touched ideally...
>>
>> You still need to "read" that bit to determine actual scheme (Top vs
>> Bottom). This is needs to be done before 2/2 enables SPI_NOR_HAS_LOCK
>> flag for macronix flashes.
> 
> Vignesh, that's the point about this commit to generalize this part about TB bit
> plus there is already exist SPI_NOR_HAS_TB flag which representing state of TB
> existence. I didn't add any support for macronix's TB bit, that's true but
> that's enough to make macronix chips able to use lock mechanism with default
> 'use_top' or any other chips which doesn't have TB bit.

Right, but 2/2 "enables" locking mechanism for Macronix flashes. Therefore its 
necessary to take TB bit into account so that implementation is correct. 
What if OTP bit is set as "use_bottom"? Although this is non default, 
we need to take care of this case for correctness.

> 
>> I guess macronix does not support SR_SRWD right? This needs special
>> treatment as well.
> 
> It does support SR_SRWD as well. No need any special treatment here.
> 

I did not find it in one Macronix datasheet at least:
https://www.macronix.com/Lists/Datasheet/Attachments/7902/MX25L25673G,%203V,%20256Mb,%20v1.6.pdf

Are you sure all Macronix flashes support SRWD?

> Thanks.
>