[PATCH v14 0/2] mtd: rawnand: Add NAND controller support on Intel LGM SoC

[Miquel Raynal]

Hello,

"Ramuthevar,Vadivel MuruganX"
<vadivel.muruganx.ramuthevar at linux.intel.com> wrote on Thu, 24 Sep 2020
16:48:40 +0800:

> This patch adds the new IP of Nand Flash Controller(NFC) support
> on Intel's Lightning Mountain(LGM) SoC.
> 
> DMA is used for burst data transfer operation, also DMA HW supports
> aligned 32bit memory address and aligned data access by default.
> DMA burst of 8 supported. Data register used to support the read/write
> operation from/to device.
> 
> NAND controller also supports in-built HW ECC engine.
> 
> NAND controller driver implements ->exec_op() to replace legacy hooks,
> these specific call-back method to execute NAND operations.
> 
> Thanks Miquel, Boris, Andy, Arnd and Rob for the review comments and suggestions.
> ---
> v14:
>   - Address Andy's review comments
>   - align the headers and revome Duplicates 
>   - replcace numerical const values by HZ_PER_MHZ and USEC_PER_SEC
>     defined macros
>   - add dev_err_probe() api instead of legacy err check
>   - add get_unaligned_le32() api instead of manual endiness
>   - remove redudent check
>   - split the lines logically in between and add require spaces
> v13:
>   - Address Miquel Raynal review comments
>   - update the return type with variable 'ret'
>   - handle err check statement properly
>   - change the naming convention aligned with recently changed the naming
>     around the data interface
>     data structure and function names
>   - replace by div 8 instead of <<4 in ecc calculation better code readability
>   - handle check_only properly like existing drivers

I am sorry but there are two to three comments which you did not
address or addressed partially while not so impacting on the logic,
can you please review and address them all? (please note that I checked
the patch adding the driver before telling you that).

Thanks,
Miquèl