[PATCH 2/2] mtd: spi-nor: Support SPI_NOR_DUAL_READ on Micron mt25qu02g.

[Tudor.Ambarus at microchip.com]

On 7/17/20 12:16 AM, David Clear wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> The Micron mt25qu02g supports both x2 and x4 transactions.  Add the
> SPI_NOR_DUAL_READ to its spi_nor_ids[] table entry.

In spi_nor_select_read() we select the fastest read. Since this flash
supports Quad Read, the Dual Read will never get selected. As of now,
there is no benefit in adding SPI_NOR_DUAL_READ when SPI_NOR_QUAD_READ
is specified.

Both SPI_NOR_DUAL_READ and SPI_NOR_QUAD_READ trigger the parsing of
SFDP, maybe we should choose to add just the fastest SPI_NOR_*_READ
supported by the flash when declaring one. We would have to update
all the flash entries. Vignesh?

> 
> Signed-off-by: David Clear <dac2 at pensando.io>
> Acked-by: Shannon Nelson <snelson at pensando.io>
> ---
>  drivers/mtd/spi-nor/micron-st.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c
> index 3dca5b9af3b6..ef3695080710 100644
> --- a/drivers/mtd/spi-nor/micron-st.c
> +++ b/drivers/mtd/spi-nor/micron-st.c
> @@ -71,8 +71,8 @@ static const struct flash_info st_parts[] = {
>                               SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |
>                               NO_CHIP_ERASE) },
>         { "mt25qu02g",   INFO(0x20bb22, 0, 64 * 1024, 4096,
> -                             SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |
> -                             NO_CHIP_ERASE) },
> +                             SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
> +                             SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
> 
>         { "m25p05",  INFO(0x202010,  0,  32 * 1024,   2, 0) },
>         { "m25p10",  INFO(0x202011,  0,  32 * 1024,   4, 0) },
> --
> 2.17.1
>