[PATCH v3 2/3] mtd: spi-nor: add 4bit block protection support

Tudor.Ambarus at microchip.com Tudor.Ambarus at microchip.com
Tue Jan 14 02:49:27 PST 2020


Hi, Jungseung,

Thanks for working on this.

On Monday, January 13, 2020 7:59:06 AM EET Jungseung Lee wrote:
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> 
> Currently, we are supporting block protection only for
> flash chips with 3 block protection bits in the SR register.
> This patch enables block protection support for some flash with
> 4 block protection bits(bp0-3).

Some? Isn't this generic for all the flashes that support BP0-3?

> 
> Signed-off-by: Jungseung Lee <js07.lee at samsung.com>
> ---
> v3 :
>   Fix wrong ofs calculation on v2 patch
> v2 :
>   Add sample table portion about 4bit block protection on the comment
>   Trivial coding style change
> 
>  drivers/mtd/spi-nor/spi-nor.c | 127 +++++++++++++++++++++++++++++-----
>  include/linux/mtd/spi-nor.h   |   8 +++
>  2 files changed, 119 insertions(+), 16 deletions(-)
> 
> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
> index e3da6a8654a8..7e8af6c4fdfa 100644
> --- a/drivers/mtd/spi-nor/spi-nor.c
> +++ b/drivers/mtd/spi-nor/spi-nor.c
> @@ -238,6 +238,14 @@ struct flash_info {
>                                          * status register. Must be used
> with * SPI_NOR_HAS_TB.
>                                          */
> +#define SPI_NOR_HAS_BP3                BIT(17) /*
> +                                        * Flash SR has 4 bit fields (BP0-3)
> +                                        * for block protection.
> +                                        */
> +#define SPI_NOR_BP3_SR_BIT6    BIT(18) /*
> +                                        * BP3 is bit 6 of status register.
> +                                        * Must be used with

Are we safe to replace SPI_NOR_TB_SR_BIT6 and SPI_NOR_BP3_SR_BIT6 with a 
SPI_NOR_SR_TB_BIT6_BP3_BIT5? Or maybe with a SPI_NOR_SR_BP3_BIT6_TB_BIT5, how 
is more convenient?

Cheers,
ta




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