[PATCH] mtd: spi-nor: Add support for w25qNNjwim

Tudor.Ambarus at microchip.com Tudor.Ambarus at microchip.com
Sat Jan 11 06:19:19 PST 2020

Hi, Michael,

On Saturday, January 4, 2020 12:34:23 AM EET Michael Walle wrote:
> Add support for the Winbond W25QnnJW-IM flashes. These have a
> programmable QE bit. There are also the W25QnnJW-IQ variant which shares
> the ID with the W25QnnFW parts. These have the QE bit hard strapped to
> 1, thus don't support hardware write protection.

There are few flavors of hw write protection supported by this flash, the Q 
version does not disable them all. How about saying just that the /HOLD 
function is disabled?

When we receive new flash id patches, we ask the contributors to specify if 
they test the flash, in which modes (single, quad), and with which controller. 
Ideally all the flash's flags should be tested, but there are cases in which 
the controllers do not support quad read for example, and we accept the 
patches even if tested in single read mode. SPI_NOR_HAS_LOCK and 
SPI_NOR_HAS_TB must be tested as well.

Even if the patches are rather simple, we ask for this to be sure that we 
don't add a flash that is broken from day one. So, would you please tell us 
what flashes did you test, what flags, and with which controller?

> Signed-off-by: Michael Walle <michael at walle.cc>
> ---
>  drivers/mtd/spi-nor/spi-nor.c | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
> index addb6319fcbb..3fa8a81bdab0 100644
> --- a/drivers/mtd/spi-nor/spi-nor.c
> +++ b/drivers/mtd/spi-nor/spi-nor.c
> @@ -2627,6 +2627,11 @@ static const struct flash_info spi_nor_ids[] = {
>  	},
> +	{
> +		"w25q16jwim", INFO(0xef8015, 0, 64 * 1024,  32,

"i" is for the temperature range, which is not a fixed characteristic. Usually 
there are flashes with the same jedec-id, but with different temperature 
ranges. Let's drop the "i" and rename it to "w25q16jwm"


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