SPI NAND bitflip threshold?

[Emil Lenngren]

Hi. I'm using UBI together with a Toshiba SPI NAND (TC58CVG1S3HRAIJ to
be specific). I'm looking into at which bitflip threshold UBI
will/should move the page. As it is now, if I read the code correctly,
it seems mtd/spi/core.c doesn't set bitflip_threshold to any specific
value so mtdcore.c sets it to ecc_strength in add_mtd_device, which to
me seems a bit high, considering my flash can correct 8 bits.

Per some discussions a long time ago
(http://lists.infradead.org/pipermail/linux-mtd/2015-January/057334.html),
raw nand currently uses 3/4 * ecc_strength as default, which seems
more reasonable.

In my flash datasheet, I can see that the default there for "ECC Bit
Flip Count Detection" is 4 bits (out of 8), which is even lower.

So my question is if the current solution should be changed to either
3/4 (or some other good default) or maybe be read from the flash
configuration registers (if supported)?

/Emil