[PATCH] mtd: spi-nor: macronix: Add post bfpt fixup for mx25u51245g

[Yicong Yang]

On 2020/12/2 19:14, Tudor.Ambarus at microchip.com wrote:
> On 12/2/20 5:59 AM, Yicong Yang wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>> The 64MB MX66U51235F's BFPT_WORD(1) declares
>> BFPT_DWORD1_ADDRESS_BYTES_3_OR_4 and it doesn't provide
>> a 4BAIT table, so the address width will be set to
>> 3-byte by default after parsing BFPT, which will make
>> the upper memory region unusable.
>>
>> As the MX66U51235F shares the same JEDEC ID with
>> MX25U51245G and is identified to MX25U51245G, add a
>> post bfpt fix hook to correct the address width in
>> MX25U51245G's entry will solve this issue. It won't
>> affect MX25U51245G which also use 4-byte address
>> width and the address width will be valided when
>> parsing its 4BAIT table.
>>
> isn't this fixed by the following commit?
>
> 324f78dfb442 ("mtd: spi-nor: Fix address width on flash chips > 16MB")

yes. I fall behind. Sorry to bother and thanks for the hint.