[PATCH 1/5] mtd: rawnand: mtk: Correct low level time calculation of r/w cycle

Miquel Raynal miquel.raynal at bootlin.com
Mon Apr 29 03:02:26 PDT 2019


Hi xiaolei,

xiaolei li <xiaolei.li at mediatek.com> wrote on Mon, 29 Apr 2019 17:35:53
+0800:

> Hi Miquel,
> 
> Thanks for your review.
> 
> 
> On Mon, 2019-04-29 at 11:03 +0200, Miquel Raynal wrote:
> > Hi Xiaolei,
> > 
> > Xiaolei Li <xiaolei.li at mediatek.com> wrote on Mon, 29 Apr 2019 14:38:30
> > +0800:
> >   
> > > At present, the flow of calculating AC timing of read/write cycle in SDR
> > > mode is that:
> > > At first, calculate high hold time which is valid for both read and write
> > > cycle using the max value between tREH_min and tWH_min.
> > > Secondly, calculate WE# pulse width using tWP_min.
> > > Thridly, calculate RE# pulse width using the bigger one between tREA_max
> > > and tRP_min.
> > > 
> > > But NAND SPEC shows that Controller should also meet write/read cycle time.
> > > That is write cycle time should be more than tWC_min and read cycle should
> > > be more than tRC_min. Obviously, we do not achieve that now.
> > > 
> > > This patch corrects the low level time calculation to meet minimum
> > > read/write cycle time required. After getting the high hold time, WE# low
> > > level time will be promised to meet tWP_min and tWC_min requirement,
> > > and RE# low level time will be promised to meet tREA_max, tRP_min and
> > > tRC_min requirement.
> > > 
> > > Fixes: 93db446a424c ("mtd: nand: move raw NAND related code to the raw/ subdir")  
> > 
> > This is definitely not the faulty patch. Please use --follow when
> > searching for the culprit, to avoid being blocked by the
> > renaming/moving work.  
> Yes. This issue exists before raw/ sudir being created.
> 
> The faulty patch should be 'commit edfee3619c49 ("mtd: nand: mtk: add
> ->setup_data_interface() hook")' which cannot be found in git history  
> now.
> 
> Should I list it here?

What do you mean? This commit exists, I can actually "git show" it.


Thanks,
Miquèl



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